Impact of fin length on threshold voltage modulation by back bias for Independent double-gate tunnel fin field-effect transistors

Mizubayashi, Wataru; Fukuda, Koichi; Mori, Takahiro; Endo, Kazuhiko; Liu, Yongxun; Matsukawa, Takashi; O’uchi, S.; Ishikawa, Yoshihiro; Migita, Shinji; Morita, Yukinori; Tanabe, Akihito; Tsukada, Junichi; Yamauchi, H.; Masahara, Meishoku; Ota, Hiroyuki

doi:10.1016/j.sse.2015.04.011

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“…For example, we examined the V th dependence of fin-type TFETs on EOT and the fin shape in Ref. 39. In our demonstrations, we utilized planar SOI-TFETs with a gate insulator having an EOT of about 1.0 nm and a gate metal of TiN.…”

Section: Device Characterizationmentioning

confidence: 99%

Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current

Mori

Asai

Fukuda

et al. 2018

Jpn. J. Appl. Phys.

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A tunnel FET (TFET) is a candidate replacement for conventional MOSFETs to realize low-power LSI. The most significant issue with the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material with a low band-to-band tunneling probability and is not favored for the channel. However, a new technology has recently been proposed to enhance the tunneling current in Si-TFETs by utilizing isoelectronic trap (IET) technology. IET technology provides an innovative approach to realizing low-power LSI with TFETs. In this paper, state-ofthe-art research on Si-TFETs with IET technology from the viewpoint of process and device integration is reviewed.

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Section: Device Characterizationmentioning

confidence: 99%