A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters

Chen, Jiajia; Tan, Jinghong; Chang, Chip-Hong; Feng, Feng

doi:10.1109/tcsi.2016.2557840

Cited by 25 publications

(16 citation statements)

References 32 publications

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“…Chen et al [20] proposed the FIR filter design that was implemented using Sensitivity Driven (SA) algorithm. The SA algorithm required a less area and power to design the FIR filter.…”

Section: Literature Surveymentioning

confidence: 99%

Low Area VLSI implementation of CSLA for FIR Filter Design

Kumar¹,

Gangappa²

2019

IJIES

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Finite Impulse Response (FIR) filter is a major building block in Digital Signal Processing (DSP) system. The conventional FIR filters are implemented by utilizing a normal adder, which consumes more area. Minimizing the hardware utilization of the adder is a significant challenge in FIR filter design. Generally, complexity of the FIR filter is dominated by the adder. So, an efficient FIR filter was designed with the help of Carry Select Adder (CSLA) to reduce area and hardware complexity of the accumulation block. The area has been reduced by using CSLA that is very significant idea while designing a less area filter. The proposed method named as Low Area-CSLA-FIR (LA-CSLA-FIR) filter. The LA-CSLA-FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) on different devices such as Virtex-4, Virtex-5 and Virtex-6 by using Verilog code. The experimental results of the LA-CSLA-FIR filter design reduced average the FPGA device utilization: 15.38 % of LUTs, 8% of flip flops and 8% of slices on Virtex-5 compared to existing filter designs.

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“…Chen et al [20] proposed the FIR filter design that was implemented using Sensitivity Driven (SA) algorithm. The SA algorithm required a less area and power to design the FIR filter.…”

Section: Literature Surveymentioning

confidence: 99%

Low Area VLSI implementation of CSLA for FIR Filter Design

Kumar¹,

Gangappa²

2019

IJIES

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“…The filtering process is the essential operation in DSP applications such as audio processing, wired/wireless communication, image, and video processing architectures [1], [2]. Digital filters play a vital role in DSP applications due to their significant performance in filtering/de-noising in mobile phones, television, the Internet etc.…”

Section: Introductionmentioning

confidence: 99%

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

Anumothu*,

Harikishore

2020

IJITEE

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In recent years, the filter is one of the key elements in signal processing applications to remove unwanted information. However, traditional FIR filters have been consumed more resources due to complex multiplier design. Mostly the complexity of the FIR filter is dominated by multiplier design. The conventional multipliers can be realized by Single Constant Multiplication (SCM) and Multiple Constant Multiplication (MCM) algorithms using shift and add/subtract operations. In this paper, a hybrid state decision tree algorithm is introduced to reduce hardware utilization (area) and increase speed in filter tap cells of FIR. The proposed scheme generates a decision tree to perform shift & addition and accumulation based on the combined SCM/MCM approach. The proposed FIR filter was implemented in Xilinx Field Programmable Gate Array (FPGA) platform by using Verilog language. The experimental results of the DTG-FIR filter were averagely reduced the 48.259% of LUTs, 51.567 % of flip flops and 44.497 % of slices at 183.122 MHz of operating frequency on the Virtex-5 than existing VP-FIR.

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“…Nowadays, various implementation and architecture methods have been presented to improve the performance of filters in terms of system complexity and speed [1]. The FIR filter used in the majority of the Digital Signal Processing (DSP) applications is based on electronic systems [2]. The FIR filter coefficients change rapidly during execution time, in several application scenarios such as a digital up-converter, digital down converter, multi-channel filter and software-defined radio systems [3,4].…”

Section: Introductionmentioning

confidence: 99%

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder

Reddy¹,

Suresh²

2018

IJIES

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Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in Software Defined Ratio (SDR) systems, whose filter co-efficient change dynamically during runtime. In this paper, Low Cost Carry Bypass adder Reconfigurable Finite Impulse Response (LC-CBA-RFIR) is introduced to perform the RFIR filter operations. DRAM-based Reconfigurable Partial Product Generators (DRPPG) consists of MUX and dual port distributed RAM, which has co-efficient to perform a FIR filter operation. With the help of Verilog code, the RFIR filter architecture was verified in Modelsim software. The same Verilog code was used to analyse the ASIC performances such as area, power and delay Area Power Product (APP), Area Delay Product (ADP) as well as FPGA performances such as LUT, flip flop, slice and frequency. After implementing ASIC and FPGA, all the performance improved in LC-CBA-RFIR method compared to the conventional methods.

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A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters

Cited by 25 publications

References 32 publications

Low Area VLSI implementation of CSLA for FIR Filter Design

Low Area VLSI implementation of CSLA for FIR Filter Design

High-Speed FIR Filter Design using Decision Tree Algorithm with FPGA Debugging

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder

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