A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

Park, Il Han; Hahn, Wook-Ghee; Song, Ki–Whan; Choi, Kiho; Choi, Hyun-Ki; Lee, Seung-Bok; Lee, Chang-Sub; Song, Jay Hyok; Han, Jin Man; Kyoung, Kye Hyun; Jun, Young-Hyun

doi:10.1109/vlsit.2012.6242442

Cited by 7 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This effect leads to an enhanced program disturb at the first WL and is usually curbed by increasing the SSL-to-WL spacing [266] or employing one [272] or two [273] dummy edge WLs. In fact, because of short-channel effects in scaled technologies, the actual electron injection point into the floating gate can move farther into the string, affecting even inner cells [274]. Moreover, such hot carriers may be trapped into the oxide and be subsequently released, giving rise to detrapping-related retention degradation [275].…”

Section: Program and Pass Disturbsmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

View full text Add to dashboard Cite

Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

show abstract

Section: Program and Pass Disturbsmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

View full text Add to dashboard Cite

show abstract

“…The NAND Flash technology scaling has introduced additional disturbance mechanisms affecting the array reliability: the cell-to-cell interference [63], [64], [65], [66] and the Gate Induced Drain Leakage (GIDL) [67], [68]. The former issue is mainly caused by the FG coupling due to parasitic capacitances between cells, thus it is greatly affected by cell scaling, and is well known to widen the V T distributions by producing read errors.…”

Section: B Reliability Effectsmentioning

confidence: 99%

“…The latter effect is due to the usage of the self-boosting technique to inhibit unselected cells during programming [69]. An electron-hole pair generation mechanism triggered by high electric fields during the program operation leads to the generation of charge in the region between the Source Line Selector (SLS) and the W L 0 that can be injected as hot electrons in the floating gate of cells belonging to W L 0 [67]. To avoid this effect, dummy wordlines need to be integrated in the array.…”

Section: B Reliability Effectsmentioning

confidence: 99%

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

et al. 2017

View full text Add to dashboard Cite

Solid-state drives (SSDs) faced an astonishing development in the last few years, becoming the cornerstone to new paradigms and markets of the information technology, such as cloud computing and big data centers. So far, the SSD design approach has focused on the optimization of the Flash translation layer, the firmware devoted to fulfill the compatibility with traditional hard-disk drives. For hyperscaled SSDs this strategy is no longer valid since their performance and reliability are strictly linked to that of the NAND Flash memories that constitute the storage medium, in particular when the multilevel cell paradigm is considered. For this reason, the design flow must follow a bottom-up approach that, starting from an accurate knowledge of the time and use dependent reliability of the NAND Flash memories, selects the most appropriate error correction strategy to extend the SSD lifetime while reducing its performance degradation. Then, the design flow moves to that of the SSD controller and of the interface toward the host where the application is running. This paper will thoroughly discuss this bottom-up approach, and finally, it will show how it is possible to leverage new approaches, such as the software-defined storage system that, by exploiting a hardware/software codesign of the SSD controller architecture and of the host application, will be able to revolutionize the traditional computer/memory interaction

show abstract

Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model

Jeon

Park

Kang

et al. 2012

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

Cited by 7 publications

References 0 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

Accurate Compact Modeling for Sub-20-nm nand Flash Cell Array Simulation Using the PSP Model

Contact Info

Product

Resources

About