A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

Atitallah, Ahmed Ben; Abid, Imen; Boudabous, Anis; Loukil, Hassen

doi:10.1002/cta.3000

Cited by 5 publications

(4 citation statements)

References 20 publications

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“…To check the proposed 1‐bit comparator and other circuits in real conditions such as digital filters, 48 they are used in image processing using the method mentioned in Sadeghi et al 5 Using this method, the CNTFET‐based transistors are directly involved with the equivalent voltage of each pixel of the input images and will produce the output voltages in the form of the expected image. Since the input images are binary and their pixels have values equal to “0” and “1,” it is expected that the output images will have exactly the values of “0” and “1.” However, due to the operation of the transistor based on the circuits' structure, the output pixels may have values between “0” to “1.” Therefore, the output images are not necessarily binary and will be gray.…”

Section: Case Study: Image Processing Using Single‐bit Comparatorsmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

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Section: Case Study: Image Processing Using Single‐bit Comparatorsmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

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“…Using a Low-Level Synthesis design, the Register Transfer Level (RTL) description may be adjusted to generate an excellent and efficient netlist. Developing an RTL description is arduous and time-consuming, particularly for complicated applications [52][53][54]. In fact, each low-level circuit's operations must be specified.…”

Section: Introductionmentioning

confidence: 99%

New Real-Time High-Density Impulsive Noise Removal Method Applied to Medical Images

et al. 2023

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This paper introduces a new method for real-time high-density impulsive noise elimination applied to medical images. A double process aimed at the enhancement of local data composed of Nested Filtering followed by a Morphological Operation (NFMO) is proposed. The major problem with heavily noisy images is the lack of color information around corrupted pixels. We show that the classic replacement techniques all come up against this problem, resulting in average restoration quality. We only focus on the corrupt pixel replacement phase. For the detection itself, we use the Modified Laplacian Vector Median Filter (MLVMF). To perform pixel replacement, two-window nested filtering is suggested. All noise pixels in the neighborhood scanned by the first window are investigated using the second window. This investigation phase increases the amount of useful information within the first window. The remaining useful information that the second window failed to produce in the case of a very strong connex noise concentration is then estimated using a morphological operation of dilatation. To validate the proposed method, NFMO is first evaluated on the standard image Lena with a range of 10% to 90% impulsive noise. Using the Peak Signal-to-Noise Ratio metric (PSNR), the image denoising quality obtained is compared to the performance of a wide variety of existing approaches. Several noisy medical images are subjected to a second test. In this test, the computation time and image-restoring quality of NFMO are assessed using the PSNR and the Normalized Color Difference (NCD) criteria. Finally, an optimized design for a field-programmable gate array (FPGA) is suggested to implement the proposed method for real-time processing. The proposed solution performs excellent quality restoration for images with high-density impulsive noise. When the proposed NFMO is used on the standard Lena image with 90% impulsive noise, the PSNR reaches 29.99 dB. Under the same noise conditions, NFMO completely restores medical images in an average time of 23 milliseconds with an average PSNR of 31.62 dB and an average NCD of 0.10.

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“…The SW component is executed by the NIOS II softcore processor, resulting in a faster filtering process but decreased reconstructed image quality. In the study [19], sequential and parallel hardware architectures are developed for the Adaptive Vector Median Filter (AVMF) using an approximated method, with a relative inaccuracy of 0.01% compared to ideal SW implementations. However, the VDF implementations in the studies [16,17] fail to satisfy real-time processing requirements, while the design in the study [18] leads to diminished denoised image quality.…”

Section: Introductionmentioning

confidence: 99%

Accelerated FPGA-Based Vector Directional Filter for Real-Time Color Image Denoising with Enhanced Performance

Alanazi¹

2023

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This paper presents an accelerated implementation of the Vector Directional Filter (VDF) on a Field Programmable Gate Array (FPGA) for real-time denoising of color images. The VDF effectively suppresses noise while preserving edges and fine details, making it ideal for a range of applications such as satellite and multispectral biomedical imaging. However, the filter's high computational complexity poses challenges for real-time processing. Existing solutions either fail to meet real-time execution requirements or compromise image quality through hardware implementation approximations. To overcome these challenges, we first model the VDF using C/C++ programming, and subsequently design an efficient floating-point hardware architecture employing the High-Level Synthesis (HLS) flow. Optimal directives are selected using the Xilinx Vivado HLS tool. The VDF architecture is then integrated as a coprocessor with the Cortex-A53 hardcore processor in the XCZU9EG FPGA. To enhance data bandwidth between software and hardware components, three Direct Memory Access (DMAs) units are utilized to transfer three image lines in parallel. Furthermore, internal memory is implemented on the XCZU9EG FPGA, providing increased flexibility for managing the restored image. The VDF Software/Hardware (SW/HW) design's robustness and accuracy are validated through experimental studies on the ZCU102 board. Our design accelerates the filtering process by 21 times, maintaining visual quality and effectively removing noise from color images compared to the VDF SW design. Additionally, our solution outperforms existing approaches in terms of filtered image quality and processing time, showing a 24% improvement in the worst-case scenario.

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A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

Cited by 5 publications

References 20 publications

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

New Real-Time High-Density Impulsive Noise Removal Method Applied to Medical Images

Accelerated FPGA-Based Vector Directional Filter for Real-Time Color Image Denoising with Enhanced Performance

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