A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Tseng, Yuan Heng; Huang, Chia-En; Kuo, Chia Wei; Chih, Yu-Der; King, Ya‐Chin; Lin, Chrong Jung

doi:10.1109/ted.2010.2089056

Cited by 21 publications

(15 citation statements)

References 7 publications

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“…RRAM stacking is realized by the TiN/TiON/SiO 2 located between the tungsten plug and N þ Si. Previous studies of the CR-RAM cell, 10,11 in which identical voltage polarities were applied during the set and reset operations, reported an extremely promising and reliable unipolar RRAM for NVM applications. However, the use of this unique CR-RAM cell is not limited to unipolar RRAM, thanks to its good bipolar switching characteristic, as demonstrated in Fig.…”

Section: Cr-ram Resistance Characteristics and Temperature Effectmentioning

confidence: 99%

“…Self compliance can be achieved with a smaller V WL for set, whereas a higher V WL ensures that there is enough reset current in the reverse direction. 11 Similarly, the group depicted by circles is realized by inversing the set and a)…”

Section: Cr-ram Resistance Characteristics and Temperature Effectmentioning

confidence: 99%

“…Building upon the RTN model developed for analyzing the conductive behavior of the gate dielectric 6,9,18 we herein statistically analyze RTN signals in contactresistive random access memory (CR-RAM) [10][11][12] to predict the electron-transport and resistive-switching characteristics, in relation to the traps in both the high-resistance state (HRS) and the low-resistance state (LRS).…”

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confidence: 99%

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Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise

Tseng¹,

Shen²,

Lin³

2012

Journal of Applied Physics

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The intense development and study of resistive random access memory (RRAM) devices has opened a new era in semiconductor memory manufacturing. Resistive switching and carrier conduction inside RRAM films have become critical issues in recent years. Electron trapping/ detrapping behavior is observed and investigated in the proposed contact resistive random access memory (CR-RAM) cell. Through the fitting of the space charge limiting current (SCLC) model, and analysis in terms of the random telegraph noise (RTN) model, the temperature-dependence of resistance levels and the high-temperature data retention behavior of the contact RRAM film are successfully and completely explained. Detail analyses of the electron capture and emission from the traps by forward and reverse read measurements provide further verifications for hopping conduction mechanism and current fluctuation discrepancies.

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Section: Cr-ram Resistance Characteristics and Temperature Effectmentioning

confidence: 99%

Section: Cr-ram Resistance Characteristics and Temperature Effectmentioning

confidence: 99%

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confidence: 99%

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Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise

Tseng¹,

Shen²,

Lin³

2012

Journal of Applied Physics

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“…As the demand for portable storage and logic nonvolatile memory (NVM) in many system-on-chip (SoC) consumer products has been emergent, the RRAM becomes more promising to be a candidate of the best solution for those issues. Especially, embedded RRAM is in the spotlight for its simplicity of fabrication and low cost [1], [5]- [7]. Because of the limitations of the compatibility between the resistive film deposition and Manuscript existing CMOS processes, it is hard to adapt the resistive film and its structure in CMOS circuits simply without impact to the CMOS logic process integration, performance, and yields [8], [9].…”

Section: Introductionmentioning

confidence: 99%

28-nm 2T High-<formula formulatype="inline"><tex Notation="TeX">$K$</tex></formula> Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Mei

Shen

et al. 2013

IEEE Electron Device Lett.

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A new two-transistor embedded resistive RAM (RRAM) cell with fully Taiwan Semiconductor Manufacturing Company 28-nm CMOS logic compatible process is reported. The new 28-nm logic compatible RRAM cell consists of two logic standard high-k metal gate (HKMG) CMOS transistors with a composite resistive gate dielectric of TiN/HfO 2 /SiO 2 /Si as a resistive memory storage node. Using one of the transistor gates as a source line in RRAM SET/RESET operation, the resistive memory states can be efficiently read and sensed by selecting the other transistor gate and its corresponding bitline. Therefore, the new 2T embedded RRAM cell has realized a logic nonvolatile memory (NVM) solution with cost effective, and fully compatible with 28-nm HKMG CMOS logic platforms. Besides, through adapting the existing high-K gate dielectric in the RRAM cell, the embedded memory cell does not need any additional deposition of resistive film or extra process steps and it will be very scalable and compatible with the fast progress of CMOS technologies in embedded NVM applications. Furthermore, its low voltage requirement makes this cell conveniently fit in logic intellectual properties and circuits for local data storages or level trimming devices on system-on-chip logic NVM products.Index Terms-28-nm high-k metal gate (HKMG) CMOS logic process, embedded resistive RAM (RRAM), nonvolatile memory.

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“…This configuration makes the linkage of resistive switching film with computation elements hard to implement and eventually leading to scaling limits. The logic-compatible contact RRAM (CRRAM) cell proposed in our previous reports [10]- [12] places the resistive switching memory element on the same level of the transistors, making the CRRAM best suited for the development of new logic units with nonvolatile memory functions. In this letter, we proposed a share CRRAM structure in combination with a sequential input operation for the realization of a nonvolatile latch (NV latch) and AND/OR logic functions.…”

Section: Introductionmentioning

confidence: 99%

Memristor Logic Operation Gate With Share Contact RRAM Cell

Shen

Tseng

Chih

et al. 2011

IEEE Electron Device Lett.

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In this letter, we proposed a novel operation of a share contact resistive random access memory (CRRAM) structure to realize a nonvolatile latch (NV latch) with a single transistor. With a share CRRAM structure and sequential input operations, the NV latch as well as AND/OR functions have been successfully demonstrated. The new mixing approach of combining memory and logic in a single unit projects the possibility of new applications for VLSI circuits.Index Terms-Contact resistive random access memory (CR-RAM), latch, logic gate.

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A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Cited by 21 publications

References 7 publications

Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise

Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise

28-nm 2T High-<formula formulatype="inline"><tex Notation="TeX">$K$</tex></formula> Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Memristor Logic Operation Gate With Share Contact RRAM Cell

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