A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier

Abstract

SummaryThe proposed booth decoder/encoder unit is an ultrahigh‐speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 μm CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate‐level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30–200% comparing related works and also improves the delay of the multiplier 4–21%. The power consumption and the area of the structure are 477 μw and 20 × 18 μm2, respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.

Design and performance analysis of an ultra‐high‐speed 5‐2 compressor

“…Figure 7 demonstrates a 16 Â 16-bit multiplier to show a typical application for the proposed 5-2 compressor. According to Fathi et al, 17,18 for 16 Â 16 bit and up multipliers, booth algorithm is usually used. As shown in this figure, there are 5-2, 4-2, FA and HA blocks in the body of the partial product tree of the multiplier.…”

High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA

“…There are variety of schemes reported in previous works 12–15 for hardware realization of this step where each scheme exhibits its own benefits and drawbacks. This paper realizes partial product (PP) generation by n bit 2 x 1 multiplexers.…”

“…In conventional multipliers, final product is obtained using full adders (FA) and half adders (HA) to add groups of PP bits. In recent works, various compression techniques like counters, compressors, and stackers are reported 12–14,16,17 . Among them, compressor‐based column reduction is proven to have modular structure with minimum latency and area efficiency 12 due to its two‐dimensional reduction of PP matrix both row wise and column wise.…”