A New Junction Termination Using a Deep Trench Filled With BenzoCycloButene

Théolier, Loïc; Mahfoz-Kotb, H.; Isoird, Karine; Morancho, Frédéric; Assié-Souleille, Sandrine; Mauran, Nicolas

doi:10.1109/led.2009.2020348

Cited by 45 publications

(11 citation statements)

References 10 publications

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“…Groove filling using a proper dielectric material, followed by a planarization process, can also be a good alternative [5].…”

Section: Resultsmentioning

confidence: 99%

“…However, the process becomes more complicated, and difficult, because trench termination is formed by a deep RIE process [5]- [7]. Manuscript The Bevel-JTE approach presented in this letter overcomes the shortcomings of the aforementioned approaches, providing a simple process flow, less area consumption, and insensitivity to process parameter variations.…”

Section: Introductionmentioning

confidence: 99%

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Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

Sung

Huang

Baliga

2015

IEEE Electron Device Lett.

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A new edge termination method, referred to as a bevel junction termination extension (Bevel-JTE), is presented for high-voltage silicon carbide devices. The 4H-SiC PiN rectifiers, with a breakdown voltage of 1600 V (∼95% of the theoretical value), were fabricated using Bevel-JTEs. The Bevel-JTE technique significantly reduces the chip size by decreasing space occupied by edge termination while providing broad process latitude for parameter variations, such as implantation dose and activation anneal condition.

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“…Groove filling using a proper dielectric material, followed by a planarization process, can also be a good alternative [5].…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

Sung

Huang

Baliga

2015

IEEE Electron Device Lett.

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“…In such cases, particularly in the case of very high-voltage devices, an appropriate junction termination extension must be implemented. Among the several suggested extension methods are selective ion implantation to modify the junction curvature [21,22], shallow-trench isolation [23], and deep-trench isolation [24].…”

Section: (D) Charge Balancementioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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“…For a 1.2kV rated structure the total lateral width around the device can be up to 450m. Fig 1(b) shows a full trench isolation using a deep trench filled with dielectric, which dramatically decreases the junction-termination area with a total lateral termination radius of up to about 100m [5]. The termination breakdown voltage is dependent on the dielectric type and can potentially suffer from Hot Carrier Injection effects due to the exposure of a large area of oxide on high electric fields.…”

Section: Introductionmentioning

confidence: 99%

Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area

Antoniou

Lophitis

Udrea

et al. 2019

IEEE Electron Device Lett.

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A new type of high voltage termination, namely the "deep p-ring trench" termination design for high voltage, high power devices is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required, it also removes the need for an additional mask as is the case of the traditional p+ ring type termination. Furthermore, the presence of the pring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide which results in reduced hot carrier injection and improved device reliability.

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A New Junction Termination Using a Deep Trench Filled With BenzoCycloButene

Cited by 45 publications

References 10 publications

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

Bevel Junction Termination Extension—A New Edge Termination Technique for 4H-SiC High-Voltage Devices

High-Voltage and Power Transistors

Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area

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