A New Low Power Flash ADC Using Multiple-Selection Method

A Cost-effective Method for Resolution Increase of the Twostage Piecewise Linear ADC Used for Sensor Linearization

“…Due to its emerging and significant application in sensor linearization, any design modification that can eliminate or minimize known drawbacks caused by the resolution increase would be of great importance. In order to perform a resolution increase in a cost-effective manner, in [8] and [9] the authors suggest introduction of one or more comparators before flash ADC to split its input range into two, four, eight or more equal sections. In this manner, only one additional comparator is needed to increase the resolution by one bit, while the flash ADC resolution remains the same.…”

“…In this paper, the resolution increase by one bit per conversion stage is performed by introducing one comparator in front of each of two flash ADCs that are composing the two-stage PWL ADC. In contrast to [8] and [9], in this paper, a comparator introduced in the first conversion stage does not split the flash ADC input range into two equal sections. In other words, difference between our design of the first stage flash ADC and the flash ADC designs proposed in [8] and [9] is in the value of a reference voltage of the comparator introduced in the first conversion stage.…”

“…In contrast to [8] and [9], in this paper, a comparator introduced in the first conversion stage does not split the flash ADC input range into two equal sections. In other words, difference between our design of the first stage flash ADC and the flash ADC designs proposed in [8] and [9] is in the value of a reference voltage of the comparator introduced in the first conversion stage. Consequently, due to the specific manner in which this voltage is set, additional modifications of the reference resistor ladder of the first stage flash ADC are required.…”

Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration

“…The following latches of stage 1 (Fig. 4) and stage 2 ( Fig.5) provide the standard CMOS voltage of digital output [4]. The simulation of the comparator is shown in Fig.7.…”

Design and performance analysis of low power ternary ADC for wide band communication

“…A ternary digit or a trit contains log 2 3 (about 1.58496) bits of information and hence more information contents can be transmitted over a given set of lines [5][6][7][8]. Using a ternary system, serial & serial-parallel operations can be carried out at higher speeds [1][2] [3]. These advantages make a ternary system gain importance in various applications like memories, communications, arithmetic circuits and signal processing [4].…”