A new low-power full-adder cell for low voltage using CNTFETs

Jitendra, Kumar; Srinivasulu, Avireni; Singh, Bhagwan

doi:10.1109/ecai.2017.8166425

Cited by 13 publications

(7 citation statements)

References 20 publications

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“…In contrast to CMOS logic, pass-transistor logic, which consists of pass transistors or pass gates, has been of great interest due to its advantage in the number of transistors. Since [9] first proposed a PTL-based FA circuit in 1992, a variety of PTL-based full adders have been proposed [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

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Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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“…Because the complete adder circuit is indispensable in any digital product, the performance of any digital circuit can be improved by enhancing it performance. Efforts to optimize performance are continuous, efforts such as the Conventional-Complementary Metal Oxide Semiconductor [1], the Removed Single Driving Full Adder (RSD-FA) [6], the Hybrid Pass Transistor Logic with Static CMOS output drive (HPSC) [3], the 18 Transistor 1-bit Full Adder [7], the Hybrid Multi-Threshold Full Adder (HMTFA) [8], and the low power based CNTFET [9]. The implementation of these adder circuits takes place using various logic families, therefore the above mentioned adders have different advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Ghabri

Issa

Samet

2019

Eng. Technol. Appl. Sci. Res.

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The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

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“…After several experimental analyses, Carbon Nanotube has been found as the most promising alternate material.The diameter of CNT is found to be between 1 to 3 nm and its length extending to a few microns. CNTFETs can be used to a high extent for building both highstrength interconnections and low resistance [4].CNTs can be exploited to build both low-resistance, highstrength interconnections and highly scalable low-power carbon Nanotube field-effect transistors (CNTFET) and single electron tunnelling transistors are one of the basic ideas to replace the silicon MOSFETs with CNTFETs to overcome all the demerits of silicon MOSFETs. The highly scalable low-power Carbon Nanotube field-effect transistors (CNTFET) and single electron tunnelling transistors are quite few among the primary ideas to take over the MOSFETs (Silicon based) with CNTFET in order to surmount the constraints of the former.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Mathan

Jayashri²,

Alias

et al. 2019

IJEEI

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VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved powerconsumption by 76.47%,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier.

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A new low-power full-adder cell for low voltage using CNTFETs

Cited by 13 publications

References 20 publications

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

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