A new profiling technique for characterizing hot carrier induced oxide damages in LDD n-MOSFET's

Lee, G.-H.; Su, Jen-Yi; Chung, Steve S.

doi:10.1016/0167-9317(95)00078-m

Cited by 3 publications

(3 citation statements)

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“…The gate oxide thickness is 7 nm. The implant is 25 keV, 3 10 cm BF , and the source/drain region was performed by using arsenic implant with an energy of 80 keV and a dose of 5…”

Section: Methodsmentioning

confidence: 99%

“…The distribution of under the maximum substrate current stress condition is well understood [5], but the comparison of peak position and quantities for between the and…”

Section: Damage Generation At Maximum Substrate Currentmentioning

confidence: 99%

“…The method by Chen et al [4] used the conventional drain-substrate junction bias method, which will impose unintentional hotcarrier damage during measurement. The numerical method in [5] needs extensive numerical calculation. Both methods can be used to determine both and under a hot electron or a hot-hole stress condition but not for both.…”

Section: Introductionmentioning

confidence: 99%

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A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions

Cheng

Yih

Yeh

et al. 1997

IEEE Trans. Electron Devices

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A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N it) and oxide charge (Q ox) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N it and Q ox in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both Nit and Qox under various bias stress conditions, such as the hot-electron stress (IG;max); IB;max; and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of Nit and Qox has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hotelectron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, E 2 PROM cells since the above stress conditions, such as the IG;max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively.

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“…The gate oxide thickness is 7 nm. The implant is 25 keV, 3 10 cm BF , and the source/drain region was performed by using arsenic implant with an energy of 80 keV and a dose of 5…”

Section: Methodsmentioning

confidence: 99%

“…The distribution of under the maximum substrate current stress condition is well understood [5], but the comparison of peak position and quantities for between the and…”

Section: Damage Generation At Maximum Substrate Currentmentioning

confidence: 99%