IntroductionThe trend to further integrate and miniaturize electronic systems generates the need to improve the diverse manufacturing technologies for heterogeneous integration, 3-Dimensional (3D) integration, advanced wafer level packaging (WLP) etc. Lithography is a key technology in down scaling and tools like wafersteppers, originally developed for early CMOS downscaling are nowadays integrated in the 3D process lines. The application of wafersteppers for 3D process integration does not require the ultimate resolution as advanced CMOS does, hence dedicated broadband illumination systems [1] or re-used I-line systems can be employed.As typical CMOS lithography is optimized for high precision, high volume production on very planar substrates, waferstepper lithography has a strong 2D nature. However, in 3D processing, substrate topography can be several hundreds of microns, resist films are sometimes very thick, leading to long exposure and development times, dual side processing is customary, etc. Therefore, the lithographic requirements for 3D micro fabrication are more diverse with significant consequences for the key litho process steps like alignment and exposure.