A new RSA cryptosystem hardware design based on Montgomery's algorithm

Yang, C.; Chang, Tian-Sheuan; Jen, Chien-Wei

doi:10.1109/82.700944

Cited by 77 publications

(1 citation statement)

References 11 publications

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“…The ciphertext can be decrypted using the private key. One of the most well-known asymmetric cryptographic algorithms was developed by Rivest-Shamir-Adleman (RSA) [1][2][3][4]. The RSA algorithm is the earliest public key cryptographic algorithm developed and published for commercial use.…”

Section: Introductionmentioning

confidence: 99%

An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

2022

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This paper presents a review of module ring learning with errors-based (MLWE-based) public-key encryption and key-establishment algorithms. In particular, we introduce the preliminaries of public key cryptography, MLWE-based algorithms, and arithmetic operations in post-quantum cryptography. We then focus on analyzing the state-of-the-art hardware architecture designs of CRYSTALS-Kyber at different security levels, including hardware architectures for Kyber-512, Kyber-768, and Kyber-1024. This analysis is dedicated to providing complete guidelines for selecting the most suitable CRYSTALS-Kyber hardware architecture to apply in post-quantum cryptography-based security systems in reality, with different requirements of security levels and hardware efficiency.

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Section: Introductionmentioning

confidence: 99%

An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

2022

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Design of a high‐speed RSA encryption processor based on the residue table for redundant binary numbers

Tomabechi

Ito²

2002

Systems & Computers in Japan

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SUMMARYThe RSA cryptosystem plays an important role in ensuring the security of network communications, although it has the drawback that much time is required for encryption/decryption. This paper presents a high-speed RSA encryption processor employing highly parallel operation based as much as possible in the hardware technology as follows: (1) All of the arithmetic circuits required for encryption/decryption are implemented in the form of redundant binary numbers. (2) Residue calculation is performed by table look-up in a hardware table built in the processor. The table look-up is done in the form of redundant binary numbers. The operation speed of the proposed processor is found to be 60 times that of usual processors when the key length N is 1024 bits. Also, the order of the encryption time of the processor is O (NlogN). The chip size of the processor is estimated as (4.3 × 10 5

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A Novel Systolic Architecture for an Efficient RSA Implementation

Moshopoulos

Pekmestzi

2001

Public Key Cryptography

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A new systolic serial-parallel scheme that implements the Montgomery multiplier is presented. The serial input of this multiplier consists of two sets of data that enter in a bit-interleaved form. The results are also derived in the same form. The design, with minor modifications, can be used for the implementation of the RSA algorithm. The circuit yields low hardware complexity and permits high-speed operation with 100% efficiency.

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A new RSA cryptosystem hardware design based on Montgomery's algorithm

Cited by 77 publications

References 11 publications

An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

An Analysis of Hardware Design of MLWE-Based Public-Key Encryption and Key-Establishment Algorithms

Design of a high‐speed RSA encryption processor based on the residue table for redundant binary numbers

A Novel Systolic Architecture for an Efficient RSA Implementation

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