A new technique for noise-tolerant pipelined dynamic digital circuits

A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

“…The ANTE metric is defined as ANTE = E(AnWn) (1) where An and W7 are the amplitude and width of the input noise pulse, respectively, and E( ) is their average. To obtain the ANTE of a dynamic circuit, it is necessary first to get its noise immunity curve.…”

“…In recent years many people have been working in techniques to improve the noise immunity in digital blocks [2] [3] [1], with low penalty in delay and low power consumption. The demand for low-power design for portable electronics has become one of the most challenging design constraints.…”

“…In order to determine which technique presents the lowest compromise between power consumption and noise immunity, in this work, three noise-immunity design techniques: Transparency Window [1], Feedback Keeper [3], and Optimized Feedback Keeper [2] are compared in terms of power consumption, ANTE, and EANTE, for different technologies. The rest of this work is organized as follows: Section II contains an overview of the three noise-immunity design techniques used in our comparison.…”

“…Furthermore, keeper techniques are suitable for all logic functions and they present low power consumption. In [1], Transparency Window technique presents the best results in noise-immunity and low power consumption when is compared with internal node precharge, source voltage raise and complementary p-network techniques.…”

A Novel Enhanced Noise-Immunity Design Technique for Dynamic Logic Gates

“…In comparison, the switching threshold voltage of static CMOS logic gate is typically around half the supply voltage [2] [3]. Therefore, dynamic logic gates inherently have less noise immunity than static CMOS logic gates and are the weak link in a high-performance VLSI chip designed using deep submicron process technology.…”