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Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noisetolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6× over conventional dynamic logic.

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (ANTE) and ANTEnormalized energy (EANTE) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35,um, 0.18,um, and 0.09,um CMOS process technologies and power supply of 3.3V, 1.8 V, and 1.0 V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.

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