Noise-tolerance improvement in dynamic CMOS logic circuits

Mendoza-Hernandez, F.; Linares-Aranda, M.; Champac, Victor

doi:10.1049/ip-cds:20050292

Cited by 37 publications

(6 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A keeper transistor is a weak transistor which supplies a small amount of current from the power supply to the dynamic node of a dynamic CMOS logic gate to prevent charge loss and to improve the noise tolerance [10].…”

Section: B Using Keepermentioning

confidence: 99%

New noise-tolerant dynamic circuit design

Jia

et al. 2009

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

View full text Add to dashboard Cite

Section: B Using Keepermentioning

confidence: 99%

New noise-tolerant dynamic circuit design

Jia

et al. 2009

2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

View full text Add to dashboard Cite

“…For example recent years, in paper [7], it proposed NC² MOS output inverter structure, which can effectively reduce the output noise of buffer. But the problem is that: i) an extra clock transistor is introduced which will suffer from larger clock load; ii) the noise is still not small enough.…”

Section: Problem Descriptionmentioning

confidence: 99%

Low-noise and power dynamic logic circuit design based on semi-dynamic buffer

Tang

Zhu

Gan

et al. 2008

2008 2nd International Conference on Anti-Counterfeiting, Security and Identification

View full text Add to dashboard Cite

Dynamic logic is one of the most important logic circuit structure. Due to precharge strategy, a lot of noise is introduced into the system as well as large extra power consumption. This paper proposes a novel structure for the buffer of the dynamic logic circuit. Using this proposed semi-dynamic logic buffer (SDB), the noise and power consumption in the buffer is dramatically deduced. Compared with the conventional buffer structure, the proposed one demonstrates much advantage in both power assumption and noise performance with roughly little drawback about driving ability.

show abstract

“…The interconnection density along with high clock frequency increases capacitive coupling of the circuit. Therefore noise pulses known as cross-talk can be generated leading to logic failure and delay of the circuit [1]. Again, when supply voltage is scaled the threshold voltage of the device needs to be scaled to preserve the circuit performance, which leads to increase in the leakage current of the device.…”

Section: Introductionmentioning

confidence: 99%

A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

Meher

Mahapatra

2013

IJCCT

View full text Add to dashboard Cite

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.

show abstract

Noise-tolerance improvement in dynamic CMOS logic circuits

Cited by 37 publications

References 14 publications

New noise-tolerant dynamic circuit design

New noise-tolerant dynamic circuit design

Low-noise and power dynamic logic circuit design based on semi-dynamic buffer

A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

Contact Info

Product

Resources

About