A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

Abstract

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (ANTE) and ANTEnormalized energy (EANTE) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35,um, 0.18,um, and 0.09,um CMOS process technologies and power supply of 3.3V, 1.8 V, and 1.0 V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.

A Novel Enhanced Noise-Immunity Design Technique for Dynamic Logic Gates

“…MK transistor draws a small amount of current from the power supply to dynamic node S, so that the charge stored in the dynamic node is maintained [1]. On the falling edge of the clock signal (CLK) the circuit enters into the pre-charge phase, the M1 transistor is ON then the dynamic node is pre-charged to a high logic level and the output Q discharges to a low logic level.…”

“…The ANTE metric is defined as the average input noise energy that the circuit can tolerate [1]. EANTE is a related parameter that quantitatively describes energy-efficiency which is the ANTEnormalized energy, given by the ratio of the average energy consumption of a circuit to its ANTE measure.…”