A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors

Safayenikoo, Pooneh; Asad, Arghavan; Mohammadi, Fazel

doi:10.1109/ccece.2017.7946731

Cited by 2 publications

(2 citation statements)

References 9 publications

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“…So, in PCMs, there are two main operations: SET operation and RESET operation. These operations are controlled by electrical current as follows: while in the RESET operation High-power are used to place the memory cell into the high-resistance RESET state, for the SET ReRAM [8-11, 17, 18, 29, 66, 72, 75, 76] STT-RAM [8,[11][12][13][14][31][32][33] [ 41,42,63,65,70,73] NAND Flash [15,16,28,37,45,46,49] [ 51,54,56,61,64] 3D XPoint [25-27, 38, 40, 43, 44, 47, 48, 50] [ 51, 52, 55, 57-60, 62, 69] operation, moderate power but longer duration pulses are used to return the cell to the low-resistance SET state. Although PCM scales well and has write endurance comparable to that of NAND Flash (10 8 -10 9 ), which makes it a viable alternate for future high-speed storage devices.…”

Section: Nvm Technologiesmentioning

confidence: 99%

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

Kargar

Nawab

2022

Distrib Parallel Databases

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Recently, non-volatile memory (NVM) technology has revolutionized the landscape of memory systems. With many advantages, such as non volatility and near zero standby power consumption, these byte-addressable memory technologies are taking the place of DRAMs. Nonetheless, they also present some limitations, such as limited write endurance, which hinders their widespread use in today’s systems. Furthermore, adjusting current data management systems to embrace these new memory technologies and all their potential is proving to be a nontrivial task. Because of this, a substantial amount of research has been done, from both the database community and the storage systems community, that tries to improve various aspects of NVMs to integrate these technologies into the memory hierarchy. In this work, which is the extended version of Kargar and Nawab (Proc. VLDB Endowment 14(12):3194–3197, 2021), we explore state-of-the-art work on deploying NVMs in database and storage systems communities and the ways their limitations are being handled within these communities. In particular, we focus on (1) the challenges that are related to high energy consumption, low write endurance and asymmetric read/write costs and (2) how these challenges can be solved using hardware and software solutions, especially by reducing the number of bit flips in write operations. We believe that this area has not gained enough attention in the data management community and this tutorial will provide information on how to integrate recent advances from the NVM storage community into existing and future data management systems.

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Section: Nvm Technologiesmentioning

confidence: 99%

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

Kargar

Nawab

2022

Distrib Parallel Databases

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“…At the same time, in this paper, we investigate the role of data encoding to reduce power in NoC instead of developing sophisticated router architectures. The data encoding scheme is another method that was employed to reduce the link power dissipation [33] [34] [45][46][47][48]. NoΔ compression [35] was proposed to reduce traffic in Network on Chip and save energy by lowering the network load.…”

Section: Related Workmentioning

confidence: 99%

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors

Safayenikoo

Asad

Mohammadi

2017

2017 18th International Symposium on Quality Electronic Design (ISQED)

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With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance challenges of 2D integration and the memory wall. However, the 3D design of SRAM LLCs has made the thermal problem even more severe. It, therefore, incurs more leakage energy consumption than conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose two different architectures that exploit the data compression to reduce the energy of LLC and interconnects in 3D-ICs. The fundamental idea of the proposed architectures is to use the non-uniform distribution of the accesses, invalid lines, zero-value lines, and frequent-value (FV) lines in banks of an LLC for decreasing both dynamic and leakage energy. The proposed architectures based on nonuniform cache architectures (NUCA) disable cache banks with low accesses and high invalid, zero, and FV lines, leading to high energy efficiency.

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A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors

Cited by 2 publications

References 9 publications

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors

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