A novel 4H–SiC SOI-MESFET with a modified breakdown voltage mechanism for improving the electrical performance

Abstract

In this paper, we present the unique features exhibited by a novel 4H-SiC silicon-on-insulator (SOI) metal-semiconductor field effect transistor (MESFET) in which the active layer consists of an insulator region (ISOI-MESFET). The key idea in this work is to make the dominant breakdown voltage mechanism to be controlled by the channel breakdown and not by the gate breakdown as a result of a high electric field at the edge of the gate near the drain. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. Our simulation results show that the breakdown voltage of the ISOI-MESFET is higher than the conventional bulk-MESFET (CB-MESFET) and conventional 4H-SiC SOI-MESFET (CSOI-MESFET). In this study, we have shown that the saturation current of the proposed structure is larger than the CB-MESFET. Also, the cut-off frequency and maximum oscillation frequency of the ISOI-MESFET improve compared to the CB-MESFET. Therefore, the ISOI-MESFET has superior dc and RF performance compared to the similar device based on the conventional structures.

Modeling a Double-Halo-Doping Carbon Nanotube FET in DC and AC Operations

“…In recent years, many efforts have been performed in order to ameliorate the conventional nanoscale SOI MOSFET by bringing up the novel configurations. [2][3][4][5][6][7][8] Although, these given structures have presented better electrical performance buy they suffer from the complexity explored by leading them into the end of the semiconductor device roadmap. The interest for the channel thicknesses less than 2 nm causes the SOI MOSFET to doesn't have qualify for operating at the low-voltage performances.…”

SiC Wafer Bonding and Deep Reactive Ion Etching Towards High-Aspect Ratio SiC MEMS Fabrication

“…The importance of this topic can be viewed through the success of silicon-on-insulator (SOI); SOI wafers expanded the versatility of Si technology by enabling devices with increased switching speed and increased radiation hardness [3] as well as a platform for MEMS devices [4]. In the same vein, silicon carbideon-insulator (SiCOI) wafers cast an even wider net, enabling SiC MEMS technology that leverages standard Si-based bulk micromachining processes [5] to produce unique device performance [6] and releasable microstructures [7]. However, in progressing towards monolithic SiC MEMS, feasible SiC wafer bonding techniques along with deep etching of high aspect ratio SiC microstructures is still needed to level the playing field between Si and SiC processing capabilities.…”

Improved multi-recessed 4H–SiC MESFETs with double-recessed p-buffer layer

“…To obtain high power density, the device must sustain large drain saturation current (I dsat ) and have high breakdown voltage (V b ). Since the I dsat is in direct proportion to the channel doping and dimensions (N Â a), a large product of the channel doping or thickness is required to allow for high drain current [6,7]. However, a higher channel doping will increase gate-source capacitance (C gs ) and a thicker channel layer will lead to lower DC transconductance (g m ), which reduces the cut-off frequency (f T ) and the maximum oscillation frequency (f max ) [8,9].…”