A novel ADPLL design using successive approximation frequency control

Eisenreich, Holger; Mayr, Christian; Henker, Stephan; Wickert, Michael; Schüffny, René

doi:10.1016/j.mejo.2008.12.005

Cited by 22 publications

(16 citation statements)

References 14 publications

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“…Defining the plasticity entirely through the waveform can also be used to substantially speed up synapse behavior in BFO up to a 50 μs time scale (You et al, 2014 ). A switched capacitor system such as (Mayr et al, 2014b ), if equipped with a scalable time base (Eisenreich et al, 2009 ), also offers the intriguing possibility of operating a high-density, CMOS-memristor hybrid neuromorphic system at varying timescales to accommodate different tasks, such as real-time interoperation with a visual sensor vs. offline, high-speed classification tasks where an accelerated timescale leads to faster classification.…”

Section: Stdp Learning Thanks To Overlapping Eventsmentioning

confidence: 99%

Plasticity in memristive devices for spiking neural networks

et al. 2015

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Memristive devices present a new device technology allowing for the realization of compact non-volatile memories. Some of them are already in the process of industrialization. Additionally, they exhibit complex multilevel and plastic behaviors, which make them good candidates for the implementation of artificial synapses in neuromorphic engineering. However, memristive effects rely on diverse physical mechanisms, and their plastic behaviors differ strongly from one technology to another. Here, we present measurements performed on different memristive devices and the opportunities that they provide. We show that they can be used to implement different learning rules whose properties emerge directly from device physics: real time or accelerated operation, deterministic or stochastic behavior, long term or short term plasticity. We then discuss how such devices might be integrated into a complete architecture. These results highlight that there is no unique way to exploit memristive devices in neuromorphic systems. Understanding and embracing device physics is the key for their optimal use.

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Section: Stdp Learning Thanks To Overlapping Eventsmentioning

confidence: 99%

Plasticity in memristive devices for spiking neural networks

et al. 2015

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“…The current clocking setup features a constant-frequency PLL (Höppner et al, 2013 ) and a clock divider, which draw constant power irrespective of the speed up factor. To save power, this could be replaced with a variable-frequency PLL with frequency-dependent power draw (Eisenreich et al, 2009 ).…”

Section: Resultsmentioning

confidence: 99%

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

et al. 2015

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Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

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“…The power dissipation of a PLL can be described as sum of a base component -due to frequency independent components, and frequency dependent component -the VCO [22,23]. To prove that the algorithm offers a low power solution, we have considered the recent All Digital PLL (ADPLL) proposed by Lee et al [24].…”

Section: Power Consumption Of Clock Generatormentioning

confidence: 99%