A novel approach for designing of variability aware low‐power logic gates

Abstract

Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters.

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

“…Remarkably, the superiorities of S-FEDs over conventional and matured technologies (e.g., FinFET) in the modulation of threshold voltage (Vth), subsequent power dissipation and noise-tolerance is emanated from (i) attuning the reservoir thickness and (ii) engineering the gates work function [39]. Standard techniques (e.g., multi-Vth interface circuit and dynamic gate-level body biasing [46]) can also be implemented in an S-FED-based design as well. This advantage is attained using silicon-based technologies, which make the integration of siliconbased circuits feasible.…”