A Novel Approach for Network on Chip Emulation

Genko, N.; Atienza, David; Micheli, Giovanni De; Benini, Luca; Mendias, J.M.; Hermida, R.; Catthoor, Francky

doi:10.1109/iscas.2005.1465100

Cited by 20 publications

(18 citation statements)

References 11 publications

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“…There are other techniques for simulation and the On-Chip verification of NoCs like the emulation technique proposed by [35]. This technique allows the emulation of NoC architectures such AETHREAL or those generated by xpipesCompiler through a standard platform.…”

Section: F Noc Emulation Techniquesmentioning

confidence: 99%

A Survey of Network-On-Chip Tools

Achballah¹,

Saoud²

2013

IJACSA

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Abstract-Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances, reliability and integration capacity. The last advantage has induced the growth of the number of cores or Intellectual Properties (IPs) in a same chip. Unfortunately, this important number of IPs has caused a new issue which is the intra-communication between the elements of a same chip. To resolve this problem, a new paradigm has been introduced which is the Network-On-Chip (NoC). Since the introduction of the NoC paradigm in the last decade, new methodologies and approaches have been presented by research community and many of them have been adopted by industrials. The literature contains many relevant studies and surveys discussing NoC proposals and contributions. However, few of them have discussed or proposed a comparative study of NoC tools. The objective of this work is to establish a reliable survey about available design, simulation or implementation NoC tools. We collected an important amount of information and characteristics about NoC dedicated tools that we will present throughout this survey. This study is built around a respectable amount of references and we hope it will help scientists.

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Section: F Noc Emulation Techniquesmentioning

confidence: 99%

A Survey of Network-On-Chip Tools

Achballah¹,

Saoud²

2013

IJACSA

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“…The ISAbased approach is very attractive for this purpose, because it can naturally map onto a hardware device to inject traffic on test chips. In [16], the potential of this type of architecture has already been shown within a field-programmable gatearray (FPGA)-based emulation platform. Compared to current ISA-based emulation and simulation approaches (using tens of instructions), our ISA is simple.…”

Section: A Ripe Isamentioning

confidence: 99%

“…The availability of built-in flow-control management lets the designer implement the same synchronization patterns, which are present in real-world applications (see Section III). Additionally, the application chunks enclosed within synchronization points can quickly be rendered by exploiting the flexible-loop structures provided by the RIPE ISA, thus providing capabilities at least on par with those of traditional stochastic trafficgenerator implementations, as shown in [10], [16], and [19]. In the very first stages of development, the RIPE can also be deployed as a validation tool to check the correct functionality of the interconnect under the load of the supported transaction types.…”

Section: Direct Developmentmentioning

confidence: 99%

“…However, as seen before, it presents an ideal tool for validation of our RIPE approach. To overcome the speedup limitation of such simulation-based approaches, an FPGAbased emulation platform has been proposed in [16]. However, the approach uses the stochastic or the trace-driven model to generate traffic, which, as addressed before, is not sufficiently accurate for MPSoC performance optimization.…”

Section: Related Workmentioning

confidence: 99%

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A Reactive and Cycle-True IP Emulator for MPSoC Exploration

Mahadevan

Angiolini

Sparsø

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bitand cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (tasksynchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context.

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“…On the other hand, FPGA based emulation solutions, have been proposed to drastically reduce the simulation and the systems evaluation time. For instance four orders of magnitude of speedup in comparison with simulation are reported in [12]. Another advantage of emulation is that, depending on the FPGA available area, it may permit to test NoCs using real applications cores instead of traffic models.…”

Section: Introductionmentioning

confidence: 99%

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Krasteva

Torre

Riesgo

2008

2008 34th Annual Conference of IEEE Industrial Electronics

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Abstract-The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.

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A Novel Approach for Network on Chip Emulation

Cited by 20 publications

References 11 publications

A Survey of Network-On-Chip Tools

A Survey of Network-On-Chip Tools

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

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