A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip

Wu, Liwei; Tang, Wei-Xiang; Hsu, Yarsun

doi:10.1109/ispa.2011.38

Cited by 11 publications

(5 citation statements)

References 8 publications

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“…Similarly, in [16] a reconfigurable NoC architecture has been proposed on which regular and application specific topologies can be implemented according to the application running by means of a configurable communication layer. The concept of router bypassing has been exploited also in [24], where the authors have proposed a Dynamic Bypass Circuit and a north-last weave routing algorithm to realize a dynamically reconfigurable NoC. Another flexible network design has been proposed in [1]: it is particularly suitable for building networks with irregular topologies, characterized by low latency and high throughput.…”

Section: Related Workmentioning

confidence: 99%

- Design Methodologies for Reconfigurable NoC–Based Embedded Systems

2018

Reconfigurable Logic

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Section: Related Workmentioning

confidence: 99%

- Design Methodologies for Reconfigurable NoC–Based Embedded Systems

2018

Reconfigurable Logic

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“…MoNoC, as the majority of works presented in this section (e.g. [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]), employs distributed monitoring based on communicating pairs of PEs, being scalable, supporting the requirements of the large amount of modules of recent and future systems.…”

Section: Related Work and Proposed Approachmentioning

confidence: 99%

MoNoC: A monitored network on chip with path adaptation mechanism

Moreno

Webber

Marcon

et al. 2014

Journal of Systems Architecture

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“…Researchers in [4][5][6][7] have proposed run-time reconfigurable topologies to introduce dynamic flexibility to communication needs. Different adaptive routing algorithms have been proposed in [8][9][10][11][12][13][14] for dynamically reconfigurable NoCs that are capable of avoiding deadlock and obstacles by bypassing faulty components. The functional examples [15] of FPGA partial reconfiguration and the accompanying design tools are in abundance.…”

Section: Introductionmentioning

confidence: 99%

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

Ijaz,

Kidane,

Bourennane

et al. 2023

Micromachines

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The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC are scaled up and down at run-time depending on the demands to connect reconfigurable IPs. The second architecture is an extension of the first, where both the rows and columns of the NoC are dynamically scaled up and down on demand. A robust control manager is developed to control the IP and sub-NoC reconfigurations by optimizing the reconfiguration costs. The proposed architectures have been implemented and tested in actual prototypes on a Virtex 6 FPGA mounted on the ML605 board. The results show that dynamically scalable architectures are capable of significant power reduction as compared to traditional static architectures for the same size of the NoC. It is anticipated that the scalable NoC can be very useful for sharing the FPGA resources among IPs at runtime.

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A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip

Cited by 11 publications

References 8 publications

- Design Methodologies for Reconfigurable NoC–Based Embedded Systems

- Design Methodologies for Reconfigurable NoC–Based Embedded Systems

MoNoC: A monitored network on chip with path adaptation mechanism

Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications

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