The continuous and rapid increase of areal density in magnetic data storage systems required a continuous increase of the coercivity of the storage media. In order to be able to record on these everhigher-coercivity media, new soft magnetic materials for pole tips with increased magnetic moment had to be developed. Significant progress has been made during the last few years in electroplating alloys with high saturation magnetic flux density for use in writing heads. We review recent progress made in this area, with particular emphasis on the work done at IBM since the review paper on the subject was published in this journal in 1998 by Andricacos and Robertson. Reviewed here are the high-moment alloys of NiFe, particularly in the very high iron range [an extension of permalloy (Ni 80 Fe 20) and Ni 45 Fe 55 ]; very-high-cobalt CoFeCu alloys; ternary CoNiFe; and binary iron-rich CoFe alloys. With the latter binary alloy films, we have demonstrated that it is possible to reach by electroplating the saturation flux density limit of 2.4-2.5 T reported for cast alloys. Since the electroplating of good-magneticquality iron-rich CoFe alloys posed a considerable challenge, the behavior of the CoFe plating system was studied in detail, using in situ surface pH measurements and a rotating-cylinder Hull cell.

Abstract-An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

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Parallel computer architectures require innovative software solutions to utilize their capabilities. This is true for system software no less than for application programs. File system development for the IBM SP product line started with the Vesta research project, which introduced the ideas of parallel access to partitioned files. This technology was then integrated with a conventional AIX environment to create the IBM AIX Parallel I/O File System product. We describe the design and implementation of Vesta, including user interfaces and enhancements to the control environment needed to run the system. Changes to the basic design that were made as part of the IBM AIX Parallel I/O File System are identified and justified.

This paper studies the memory system behavior of Java programs by analyzing memory reference traces of several SPECjvm98 applications running with a Just-In-Time (JIT) compiler. Trace information is collected by an exceptionbased tracing tool called JTRAeE, without any instrumentation to the Java programs or the JIT compiler.First, we find that the overall cache miss ratio is increased due to garbage collection, which suffers from higher cache misses compared to the application. We also note that going beyond 2-way cache associativity improves the cache miss ratio marginally. Second, we observe that Java programs generate a substantial amount of short-lived objects. However, the size of frequently-referenced long-lived objects is more important to the cache performance, because it tends to determine the application's working set size. Finally, we note that the default heap configuration which starts from a small initial heap size is very inefficient since it invokes a garbage collector frequently. Although the direct costs of garbage collection decrease as we increase the available heap size, there exists an optimal heap size which minimizes the total execution time due to the interaction with the virtual memory performarLce.