An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Liu, Chih-Hao; Yen, Shau-Wei; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen‐Yi; Hsu, Yarsun; Jou, Shyh-Jye

doi:10.1109/jssc.2007.916610

Cited by 117 publications

(55 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In this paper, we devised an efficient circuit for generating shift values of 108 PCMs as shown in Fig. 3 direct implementation using LUTs in [15] and [17].…”

Section: Overall Architecturementioning

confidence: 99%

“…The 2-bit SM indicates the sign (i.e., positive or negative) and the type of minimum (i.e., min0 or min1). The basic concept for storing the CN messages in a compressed way is similar to the method in [17][18][19], but our CN memory structure and implementation are different from them. Since CN memory does not store all the min0s, we need to restore the 2's complement value of each CN message using the Mag_min0s, Mag_min1s and SM information stored in the CN memory.…”

Section: Check Node Memorymentioning

confidence: 99%

See 1 more Smart Citation

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Shin¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-m CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V

show abstract

“…In this paper, we devised an efficient circuit for generating shift values of 108 PCMs as shown in Fig. 3 direct implementation using LUTs in [15] and [17].…”

Section: Overall Architecturementioning

confidence: 99%

Section: Check Node Memorymentioning

confidence: 99%

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Shin¹,

Kim²

2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…The proposed partially-parallel irregular LDPC decoder architecture was Fig. 3.c shows the proposed structure has great advantages on area compared with [4,5,6,7]. Its normalized area is only 0.075.…”

Section: Early Termination Strategymentioning

confidence: 99%

“…Several proposed LDPC architectures including fully-parallel decoder [4], partially-parallel decoder [5,6,7,8] etc. From these state-of-arts, partiallyparallel provides an effective trade-off between hardware cost and throughput and widely is chosen in the decoder design.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a multi-rate and multi-size LDPC decoder

Chen

Xiong

et al. 2009

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:A fully reconfigurable architecture of a LDPC (lowdensity parity check) decoder for IEEE 802.11n system is proposed in this paper. This architecture can be operated in 12 kinds of modes specified in IEEE 802.11 system. Under the proposed architecture, memory usage and hardware complexity obviously improved, as compared with the other research works. Furthermore, the proposed decoder also able to support multi-rate and multi-size LDPC codes decoding. The proposed decoder was implemented in UMC 0.18 μm CMOS technology. The maximum operating frequency is measured 200 MHz and the corresponding power dissipation is 691.23 mW and total area is 4.61 mm 2 . Keywords: IEEE 802.11n, LDPC decoder, layered belief propagation, early termination, reconfigurable Classification: Electron devices, circuits, and systems [1] IEEE 802.11n Wireless LAN Medium Access Control MAC and Physical Layer PHY specification, IEEE 802. 11n-D1. 0, 2006 [2] J. Chen and M. P. C. Fossorier, "Near optimum universal belief propagation based decoding of low-density parity-check codes," IEEE Trans. References

show abstract

“…However, different Z (Maximum memory conflict-free parallel decoding sublayers) will lead to the adjustment of parallelism of the decoder. The decoder with parallelism P can easily support decoding QC-LDPC codes with Z ≤ P. Therefore previous schemes often apply a Z-parallelism as the hardware structure [3] [4] [5] in order to satisfy Z ≤ P. For the case of Z > P, several solutions are proposed in the literature review however have not be extended to support arbitrary Z. For example, Kuo et al [6] proposed a shift network with 24 parallelism which is compatible for Z ≤ 96, but it is only considered for the Z parameters given in IEEE 802.16e.…”

Section: Introductionmentioning

confidence: 99%

A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

Wang¹,

Wu²,

Li³

et al. 2017

IJCNS

View full text Add to dashboard Cite

The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z  P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.

show abstract

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Cited by 117 publications

References 16 publications

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

Implementation of a multi-rate and multi-size LDPC decoder

A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

Contact Info

Product

Resources

About