A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders

Abstract

This paper presents an efficient architecture design for Elementary Check Node processing in Non-Binary Low-Density Parity-Check decoders based on the Extended Min-Sum algorithm. This architecture relies on a simplified version of the Bubble Check algorithm and is implemented by the means of FIFOs. The adoption of this new design at the Check Node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied FPGA surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.

Hybrid Check Node Architectures for NB-LDPC Decoders

“…A serial hardware implementation of the Bubble CN architecture was presented in [20]. Suboptimal versions considering only the subset of the most probable potential bubbles (the first two rows and two columns) were presented in [20], [21] and [22].…”

“…• S-xB: with x > 1, also known as S-bubble ECN. As described in [22], this architecture compares x bubbles per clock cycle. In Fig.…”

“…12 shows the obtained Frame Error Rate (FER) for a GF(64) code of size (864,720) bits, code rate R = 5/6, d c = 12 and d v = 2 over the Gaussian channel. We consider the FB decoder in [22] as a reference, i.e. S-bubble algorithm with 4 bubbles, n m = 16 and n op = 18.…”

“…14 shows performance results for a GF(256)-LDPC code of size (1152, 960) bits, code rate R = 5/6, d c = 12 and d v = 2. We consider as a reference the FB decoder with a S-bubble architecture [22], 6 bubbles, n m = 40 and n op = 45. The HB(5, 5, 2) architecture presents the same performance as the FB and the HB(5, 6, 1) shows slight performance loss smaller than 0.05 dB.…”

“…15 shows performance results for a GF(64) (1536, 1344) LDPC code, code rate R = 7/8, d c = 16 and d v = 2. As reference, we consider the FB decoder with a S-bubble architecture [22], 4 bubbles, n m = 16 and n op = 18. The architecture being used is the same as the one presented in Fig.…”