A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity

Adams, M.; Toumazou, C.

doi:10.1109/iscas.1995.521440

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…. It is shown in [40] that these conditions are met if each switching block satisfies the following two-part Number Conservation Rule: the two outputs of each switching block must be in the range where is the layer number, and their sum must equal the input to the switching block (4) From (1) and (4), the input/output relationships of switching block are and…”

Section: Constraints On the Switching Sequencementioning

confidence: 99%

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Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters

Welz

Galton

Fogleman

2001

IEEE Trans. Circuits Syst. II

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Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta-sigma data converters because they facilitate delta-sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in delta-sigma analog-to-digital converters the mismatch-shaping logic is in the feedback path of the delta-sigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatch-shaping logic. This paper presents and analyzes several variations of the switching blocks within a tree-structured mismatch-shaping DAC that result in the most hardware-efficient first-order and second-order mismatch-shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagation-delay reduction so as to tailor designs to specific applications.

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Section: Constraints On the Switching Sequencementioning

confidence: 99%

“…The XOR tree is a consequence of the functional relationship between the outputs of a switching block and its input. From (4), the values of the output sequences of a switching block must add to the value of the input. Thus, the parity of can be determined by the parities of and…”

Section: B the High-speed Switching Blockmentioning

confidence: 99%