Noise-shaped multbit D/A convertoremploying unit elements

Schreier, Richard; Zhang, B.

doi:10.1049/el:19951194

Cited by 152 publications

(55 citation statements)

References 3 publications

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“…The non-linearities in the DAC are one of the critical bottlenecks for the overall performance of the ADC. In order to cope with these non-linearities, various dynamic element matching (DEM) techniques have been used, for example, [76][77][78][79][80][81][82][83][84][85][86][87][88][89]. A disadvantage of the DEM is that size and power consumption grow exponentially with the increased word length and higher resolution of the digital feedback signal.…”

Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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Section: Motivationmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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“…In order to overcome the undesirable effects of unit element mismatches, mismatch-shaping Dynamic Element Matching (DEM) techniques have been developed [1]- [3]. These techniques manipulate the usage of elements of a multibit DAC in such a way that the error caused by mismatches is being filtered and spectrally shaped.…”

Section: Introductionmentioning

confidence: 99%

A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators

Lavzin

Kozak

Friedman

2008

2008 IEEE International SOC Conference

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Abstract-Mismatch-shaping Dynamic Element Matching (DEM) methods are extensively used in multi-bit Sigma-Delta Modulators (SDM) to reduce the effects of element mismatches. To date, only first and second-order mismatch-shaping DEM techniques have been reported in the literature. In this paper, a higher-order mismatch-shaping DEM method is reported, which is an extension of the known vector-feedback mismatch-shaping technique. Example simulation results are presented for thirdorder and fourth-order mismatch-shaping DEMs.

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“…The alternative possibility for increased SNR, i.e., employing a high-order loop filter, would result in potential stability problems and high sen sitivity to coefficient variations. The inherent DAC nonlinear characteristic, which is the main drawback of multi-bit quan tizers, can be compensated using dynamic element matching techniques [2], [3]. Second, the loop-filter of the ADC is implemented as a continuous-time (CT) circuit.…”

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confidence: 99%