A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators

Lavzin, A.; Kozak, M.; Friedman, Eby G.

doi:10.1109/socc.2008.4641525

Cited by 7 publications

(3 citation statements)

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“…However, realizing DEM designs of order >2 in lowpass and >4 in bandpass is difficult to achieve. In [5], the authors outline the use of a ∆∑ modulator structure to provide high order mismatch shaping in a vector feedback DEM design. The work in [6] details a significant advancement with the development of a 4 th order lowpass vector feedback DEM.…”

Section: Introductionmentioning

confidence: 99%

High Order Mismatch Shaping for Low Oversampling Rates

O'Brien

Mullane

2020

IEEE Trans. Circuits Syst. II

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Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current high order DEM decoders provide little or no improvement in error suppression over lower order designs. In addition, the logic requirement of the DEM decoder increases significantly with each additional DAC bit. This paper presents a high order DEM decoder that improves mismatch shaping performance at low to medium oversampling rates by up to 15dB, while employing methods to reduce the area overhead of the vector quantizer in the design.

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Section: Introductionmentioning

confidence: 99%

High Order Mismatch Shaping for Low Oversampling Rates

O'Brien

Mullane

2020

IEEE Trans. Circuits Syst. II

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“…Several DEM techniques exist such as Data Weighted Averaging (DWA) [1], Butterfly-shuffler [2], Tree structure [3] and Vector Feedback [4] but so far the mismatch shaping provided by these schemes is limited to second order. Research has shown that Vector Feedback DEM has the potential to provide higher orders of mismatch shaping [5], however hardware designs with stable implementations or orders greater than 2 remain difficult to achieve for high frequencies and low silicon area overheads. In particular, the area occupied by the DEM circuitry is known to increase exponentially with higher N-bit DAC sizes and this typically limits the number of bits in the DAC to between 4 and 6 [6].…”

Section: Introductionmentioning

confidence: 99%

VLSI-SoC: Advanced Research for Systems on Chip

2012

IFIP Advances in Information and Communication Technology

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Abstract. Direct Digital Synthesis (DDS) systems generate fine frequency resolution signals over a broad spectrum that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance DDS band-pass Digital to Analog Converter (DAC) architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power D/A Converter is portable to standard CMOS processes and designed to achieve over 100dB narrow-band SFDR performance using Sigma-Delta (∑Δ) modulation and multi-bit current steering techniques. A 3 rd order digital ∑Δ modulator is combined with a 4 th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.

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“…The solution to this is to use higher order DEM schemes, however the implementation of these schemes is not trivial as orders greater that 2 suffer from instability. One method of using higher order noise shaping is presented in [5]. Here the author demonstrates behavioral simulations of 4th order noise shaping filters that achieve very high resolutions for low-pass signals when dealing with a static mismatch of 1%.…”

Section: Introductionmentioning

confidence: 99%