2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) 2014
DOI: 10.1109/mixdes.2014.6872171
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A novel fast glitchless 7-3 counter with a new structure

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Cited by 6 publications
(4 citation statements)
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“…This counter is composed of four full adders. In Ghasemzadeh, Mohabbatian, Akbari, Hadidi, and Khoei (2014), a novel CMOS structure for the 7-to-3 counter is designed. In this design, the outputs are based on the number of bits with value '1' in truth table.…”
Section: Counter Cellsmentioning
confidence: 99%
“…This counter is composed of four full adders. In Ghasemzadeh, Mohabbatian, Akbari, Hadidi, and Khoei (2014), a novel CMOS structure for the 7-to-3 counter is designed. In this design, the outputs are based on the number of bits with value '1' in truth table.…”
Section: Counter Cellsmentioning
confidence: 99%
“…By utilizing the proposed booth encoder structure in a 16x16 pipelined multiplier together with a 4-2 compressor [12], [13] as a load, and also using a random input data, the simulation result which is depicted in fig. 8 will be close to the practical result.…”
Section: Proposed Circuitmentioning
confidence: 99%
“…Another method is called carry look ahead adder (CLA) which is used in many articles [6]. To lower the latency of the mentioned step, 7-2 compressors have been widely employed nowadays for high speed multipliers [7][8][9][10][11][12][13]. Basic structure of a 7-2 compressor is depicted in Fig.…”
Section: Introductionmentioning
confidence: 99%
“…(1), 7-2 compressors of [9], [10 ], and [11] are designed. Also, 7-2 compressors can be constructed by threshold logics (TL) and three-level MOS current-mode Logic (MCML) gates [7].…”
Section: Introductionmentioning
confidence: 99%