A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

Chang, Kang-Ming; Lin, Gin Min; Chen, Cheng Guo; Hsieh, Ming‐Feng

doi:10.1109/led.2006.887933

Cited by 8 publications

(8 citation statements)

References 11 publications

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“…The contact resistance of direct contacted poly-Si/ITO/SD TFT was 9.0×10 6 , which was 4 orders higher than the conventional TFT. By using the side contact, the contact resistance was reduced to 3.7×10 3 , which was close to normal level. In addition, the mobility of ring contacted poly-Si/ITO/SD TFT can also comparable to that of the conventional TFT.…”

Section: Resultssupporting

confidence: 57%

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P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

Luo

He²,

Xu³

et al. 2020

Symp Digest of Tech Papers

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A novel six-mask LTPS TFT architecture is fabricated and used in TFT-LCD. The light shielding layer and organic layer are removed. Furthermore, the pixel indium tin oxide and source drain patterns are developed in one halftone mask. To solve the issue of high photo leakage current, we have investigated the generation mechanism of Iphoto and established guidelines for reducing it. The optical and electrical characteristics of the sixmask TFT-LCD are comparable to those of conventional TFT-LCD.

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Section: Resultssupporting

confidence: 57%

“…Thus, conventional products have inevitably high cost of process and also investment, which increases product cost. To be more competitive on the market, it is strongly required for LTPS TFTs products to have reduced photomask steps and, thus, simplified processes in manufacturing [3,4].…”

Section: Introductionmentioning

confidence: 99%

P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

Luo

He²,

Xu³

et al. 2020

Symp Digest of Tech Papers

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“…Although a thicker drain region causes the generation volume of the D-SAGRSD TFT to increase, the maximum lateral electric field near the drain region of the D-SAGRSD TFT, as shown in Fig. 3, is also dropped from 1.11 to 1.00 MV/cm due to thick source/drain regions [10], [14]. At higher drain and reverse gate biases (V ds = 5 V and V gs = −15 V), the leakage current would be due to the thermionic field emission via grain boundary defects [15].…”

Section: Resultsmentioning

confidence: 97%

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

Chang

Lin

Yang

2007

IEEE Electron Device Lett.

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In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower OFF-state current (177 to 6.29 nA), and the ON/OFF current ratio is only slightly decreased from 1.71 × 10 7 to 1.39 × 10 7 . Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications. Index Terms-Damascene process, four masks, on/off current ratio, polycrystalline silicon thin-film transistor (poly-Si TFT), raised source/drain (RSD), self-aligned gate, thin channel.

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“…To achieve this ideal TFT structure, we have proposed a novel four-mask step TFT structure with self-aligned raised source/drain (SARSD) [7]. In the SARSD TFT structure, a special structure was formed, which had a wide channel width and a narrow source/drain width.…”

Section: Effect Of Channel-width Widening On Amentioning

confidence: 99%

“…In the SARSD TFT structure, a special structure was formed, which had a wide channel width and a narrow source/drain width. A high ON-state drain-current was obtained due to low channel resistance and additional current-flow paths existing in the side-channel regions [7]. Several models have been proposed to explain the behavior of the ON-state drain-currents of poly-Si TFTs and to simulate these ON-state drain-current values [8]- [11].…”

Section: Effect Of Channel-width Widening On Amentioning

confidence: 99%

Effect of Channel-Width Widening on a Poly-Si Thin-Film Transistor Structure in the Linear Region

Chang

Lin

2007

IEEE Trans. Electron Devices

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This is the first paper to discuss the ON-state drain-current of a special thin-film transistor structure with a wide channel width and a narrow source/drain width in the linear region. The experimental results indicate that when the channel width is wider than the source/drain width, the side-channel current effect is generated. This effect increases the ON-state drain-current due to the additional current-flow paths existing in the side-channel regions and low channel resistance. As the side-channel width increases, the ON-state drain-current initially increases and then gradually becomes independent of the side-channel width when the side-channel width is larger than the effective side-channel width, which depends on the channel width and is largely independent of the source/drain width. This paper also demonstrates that the ON-state drain-current gain is directly proportional to the channel length and the ratio of the channel length to the source/drain width and dependent on the side-channel width.Index Terms-Drain-current, poly-Si thin-film transistor (TFT), source/drain width, wide channel width. I. INTRODUCTIONL OW-TEMPERATURE polycrystalline-silicon thin-film transistors (TFTs) are one of the most promising technologies for the ultimate goal of building large-area electronic systems on glass substrates [1]. In flat-panel liquid-crystal, electroluminescence, and plasma displays, as well as other applications such as high-speed printers and page-width optical scanners, poly-Si TFTs can be utilized to integrate peripheral driver circuits on glass for system integration [2]. To integrate peripheral driving circuits on the same glass substrate, a large current drive and a high drain breakdown voltage are necessary for poly-Si TFT devices. Previous studies reported that use of a thin active-channel film is beneficial in obtaining a high current drive [3], [4]. However, the use of a thin activechannel layer typically results in poor source/drain contact and large parasitic series resistance. A thick source/drain region not only reduces the lateral electric field, thus maintaining the Manuscript

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A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

Cited by 8 publications

References 11 publications

P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

P‐52: A Novel Six‐Mask Low‐Temperature Polycrystalline Silicon Architecture for TFT‐LCD Application

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

Effect of Channel-Width Widening on a Poly-Si Thin-Film Transistor Structure in the Linear Region

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