A novel framework for multilevel full-chip gridless routing

Abstract

Abstract-Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult than grid-based routing because of its larger solution space. In this paper, we present a novel "V-shaped" multilevel framework (called VMF) for full-chip gridless routing. Unlike the traditional "Λ-shaped" multilevel framework (inaccurately called the "Vcycle" framework in the literature), our VMF works in the V-shaped manner: top-down uncoarsening followed by bottom-up coarsening. Based on the novel framework, we develop a multilevel full-chip gridless router (called VMGR) for large-scale circuit designs. The top-down uncoarsening stage of VMGR starts from the coarsest regions and then processes down to finest ones level by level; at each level, it performs global pattern routing and detailed routing for local nets and then estimate the routing resource for the next level. Then, the bottom-up coarsening stage performs global maze routing and detailed routing to reroute failed connections and refine the solution level by level from the finest level to the coarsest one. We employ a dynamic congestion map to guide the global routing at all stages and propose a new cost function for congestion control. Experimental results show that VMGR achieves the best routability among all published gridless routers based on a set of commonly used MCNC benchmarks. Besides, VMGR can obtain significantly less wirelength, smaller critical path delay, and smaller average net delay than the previous works. In particular, VMF is general and thus can readily apply to other problems.

Low-power gated clock tree optimization for three-dimensional integrated circuits

“…We generate topological gated clock tree based on the multilevel framework [17] for better scalability, consisting of three major stages: To determine the position of a partition wall, we sweep the wall along its perpendicular direction, and construct a minimum spanning tree (MST) for each flip-flop group on both sides of the wall. The cost of an MST is calculated based on the capacitance of wires and TSVs.…”

The coming of age of (academic) global routing

“…Multi-level techniques, now commonly used in placement [4,7,21], have not proven as effective in global routing as flat techniques. However, their counterparts in gridless and detailed routing [8,9,14] will likely continue to offer significant runtime savings.…”

An ILP based hierarchical global routing approach for VLSI ASIC design

“…Inspired by the successful application of multilevel methods in circuit partitioning and placement a top-down hierarchical routing algorithm would attempt to use a hierarchy on the routing graph to decompose the large routing problem into smaller and more manageable pieces. There are several approaches to hierarchical global routing (14): top-down hierarchical routing, bottom-up hierarchical routing and multilevel global routing (3)(4)(5). All of these methods attempt to solve the scaling problem of large designs by building multilevel hierarchical representations of the routing regions.…”