A novel guard method of through-silicon-via (TSV)

Zhu

et al. 2018

With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and the MOS capacitance variation is the main reason for the change of TSV capacitance and the TCC increases with elevated temperature. Furthermore, the affection of TSV dimensions on TCC are discussed. It is shown that the TCC increases gradually as the TSV radius increases, while the thickness of dielectric layer is the opposite. The cylinder TSV is less thermal sensitive than tapered TSV. This paper provides basis for TSV design considering the temperature effect.

Section: Temperature Coefficient Of C Tsvmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

Zhu

et al. 2018

“…In the design of integrated circuits (ICs) for RF applications, vias are generally still considered as RC elements [1,2,3,4]. However, as the operation frequency of ICs increases, the inductive behavior of on-silicon vias (OSV) and vertical interconnections must be considered as in the case of PCB, RDL, and TSV technologies [5,6,7,8,9,10]. The previously performed analyses reported in [11,12] included the characterization of the electromagnetic behavior of via arrays and stacks; in this case, however, the results were obtained only through full-wave simulations.…”

Section: Introductionmentioning

confidence: 99%

Characterization and modeling of on-chip via stacks for RF-CMOS applications

Diaz

Aranda

Torres‐Torres

et al. 2020

This work proposes an experiment-based characterization and modeling approach for interconnection channels including via stacks as vertical transitions. A daisy chain structure implemented in a 0.18 µm RFCMOS process is used for developing and verifying the validity of the proposal. The usefulness of the models is shown by assessing the impact of the vias in a practical resonant rotary traveling wave oscillator (RTWO). The oscillation frequency of the RTWO is reduced 13.7% when the via stack models are included.

“…For resolving this problem, some kinds of techniques come out. One is through-silicon via (TSV) that is ordinarily termed as vertical interconnection [5,6,7,8,9]. The capacitor in terms of TSV is different from typical capacitor due to its small area and adapt to current IC manufactured process.…”

Section: Introductionmentioning

confidence: 99%

A high-pass filter based on through-silicon via (TSV)

Wang

Huang

2019

Self Cite

A fourth-order high-pass filter is proposed, which is formed by spiral inductors and TSV capacitors. The components of this filter rely on the TSV technology, which is generally regarded as vertical interconnection but now used to compose capacitor. The comparison of the results between finite element method and equivalent electric circuit obviously proves that they have nearly equal filtering characteristics including cutoff frequency and roll-drop rate. Moreover, the comparisons are made among the HPFs based on different technologies, and the challenges the proposed HPF faces are discussed.