A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulation

Park, J.-H.; Kwon, Sin; Bae, Byoung-Jae; Kim, I.; Ji, Nan; Lee, K.; Shin, Hong-Jae; Han, Shin-Hee; Hwang, Soonkyu; Jeong, Dong Seop; Lee, J.; Oh, Sechang; Park, S. O.; Song, Y. J.; Jeong, Gitae; Koh, G.H.; Hyun, Seok-Hun; Hwang, Kyusung; Nam, Seok Woo; Kang, Ho-Kyu; Jung, Eui S.; Jeong, Jooyeon; Pi, Ung Hwan; Kim, W.K.; Lee, Jangwook; Noh, Enu-Hee; Kim, K.; Lim, Woo Hyun

doi:10.1109/iedm19573.2019.8993614

Cited by 15 publications

(8 citation statements)

References 6 publications

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“…We keep monitoring the film thicknesses periodically to ensure 2% of wafer-to-wafer variations. Overall film stacks, especially for the MgO tunneling barrier/CoFeB interfaces, are well stacked with sharp interfaces confirmed by the TEM [46] thanks to the surface treatment by the chemical mechanical polishing process. Detailed information of the integration procedures and isolated device performance can be found in our-previous work [46] .…”

Section: Methodsmentioning

confidence: 67%

“…In our previous work, we successfully integration isolated SOT-MTJs in a 200 mm-wafer R&D platform, achieving uniform electrical and magnetic performance across the wafer [46] . In addition, high endurance of up to 10 12 cycles was achieved for the fabricated isolated SOT-MTJs [28,46] . Building upon this achievement, we further integrated the SOT-MTJs into an array in conjunction with CMOS in the 200 mm wafer.…”

Section: Introductionmentioning

confidence: 99%

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Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications

Jiang,

Li,

Zhang

et al. 2023

J. Semicond.

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We have successfully demonstrated a 1 Kb spin-orbit torque (SOT) magnetic random-access memory (MRAM) multiplexer (MUX) array with remarkable performance. The 1 Kb MUX array exhibits an in-die function yield of over 99.6%. Additionally, it provides a sufficient readout window, with a TMR/R P_sigma% value of 21.4. Moreover, the SOT magnetic tunnel junctions (MTJs) in the array show write error rates as low as 10−6 without any ballooning effects or back-hopping behaviors, ensuring the write stability and reliability. This array achieves write operations in 20 ns and 1.2 V for an industrial-level temperature range from −40 to 125 °C. Overall, the demonstrated array shows competitive specifications compared to the state-of-the-art works. Our work paves the way for the industrial-scale production of SOT-MRAM, moving this technology beyond R&D and towards widespread adoption.

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Section: Methodsmentioning

confidence: 67%

Section: Introductionmentioning

confidence: 99%

Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications

Jiang,

Li,

Zhang

et al. 2023

J. Semicond.

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“…At this scaled ∆ and I r , the read latency can also be scaled by adjusting the sense amplifier reference voltage [6], [18]. Equation (15) implies that at scaled ∆, the shortened read pulse duration will also ensure that the Read Disturb rate is within the acceptable target.…”

Section: Optimizing Stt-mram For Ai Acceleratorsmentioning

confidence: 99%

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

Mishty

Sadi

2021

IEEE Trans. VLSI Syst.

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In this paper, we demonstrate the design of efficient and high-performance AI/Deep Learning accelerators with customized STT-MRAM and a reconfigurable core. Based on modeldriven detailed design space exploration, we present the design methodology of an innovative scratchpad-assisted on-chip STT-MRAM based buffer system for high-performance accelerators. Using analytically derived expression of memory occupancy time of AI model weights and activation maps, the volatility of STT-MRAM is adjusted with process and temperature variation aware scaling of thermal stability factor to optimize the retention time, energy, read/write latency, and area of STT-MRAM. From the analysis of modern AI workloads and accelerator implementation in 14nm technology, we verify the efficacy of our designed AI accelerator with STT-MRAM (STT-AI). Compared to an SRAMbased implementation, the STT-AI accelerator achieves 75% area and 3% power savings at iso-accuracy. Furthermore, with a relaxed bit error rate and negligible AI accuracy trade-off, the designed STT-AI Ultra accelerator achieves 75.4%, and 3.5% savings in area and power, respectively over regular SRAM-based accelerators.

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“…These memories have high read/write current densities as compared to conventional CMOS memory technologies such as the Static Random Access Memory (SRAM) and hence are more susceptible to EM effects. In this work, we focus on EM analysis in the STT-MRAM technology since it is more mature as shown by several recent industrial demonstrations [14][15][16][17].…”

Section: A Spintronic Memory Technologymentioning

confidence: 99%

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Nair

Mayahinia

Tahoori

et al. 2021

IEEE Trans. Device Mater. Relib.

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Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronicbased memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workloaddependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

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A novel integration of STT-MRAM for on-chip hybrid memory by utilizing non-volatility modulation

Cited by 15 publications

References 6 publications

Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications

Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

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