A novel interconnect optimal buffer insertion model considering the self-heating effect

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.

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“…There fore the optimal delay per unit length can be obtained, (Yan et al, 2013;Narasimhan and Sridhar, 2010) Equation (16) …”

Section: Delay and Bandwidth Interconnectionsmentioning

confidence: 99%

A Particle Swarm Optimization Approach for Low Power Very Large Scale Integration Routing

Nallathambi¹,

Rajaram²

2014

Journal of Mathematics and Statistics

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Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

Zhang

2018

Wuhan Univ. J. Nat. Sci.

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Power aware VLSI routing using particle swarm optimization for green electronics

Nallathambi

Rajaram

2014

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

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Energy power dissipation is one of the most critical aspects of todays information society. The most obvious benefits of being Green are reduced environmental impact and cost savings. Reducing energy consumption of electronic devices and circuits .This paper deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in deep submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion, (Buffer) Sizing and Wire Sizing (BISWS) are considered for minimizing the power dissipation using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are considered for analysis the optimal power allocation is derived. The Particle swarm optimization algaritham can be used to efficiently estimate the power dissipation in the stages of the VLSI designs. It is observed that the power dissipation is optimal using the shortest path between source to sink.

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A novel interconnect optimal buffer insertion model considering the self-heating effect

Cited by 3 publications

References 9 publications

A Particle Swarm Optimization Approach for Low Power Very Large Scale Integration Routing

A Particle Swarm Optimization Approach for Low Power Very Large Scale Integration Routing

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

Power aware VLSI routing using particle swarm optimization for green electronics

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