tures. The frequency domain behaviors of the unit cells are characterized using S-matrix files. Simulation results have been compared to measurements on a benchmark structure fabricated in LTCC. The transmission line approach requires 30 minutes with good agreement between simulation and measurement results up to 9 GHz for a 2.5 mm grid pitch and up to 16 GHz for a 1 mm grid pitch. A comparable full wave simulation using Ansoft's HFSS requires more than 100 hours to accurately model the frequency domain behavior of the whole structure. [6]. In this paper, based on the results of RF power n-MOSFETs for system on chip (SOC) applications, the third origin of the S 22 kink phenomenon in deep sub-micron RF MOSFETs, that is, small-signal gate-drain resistance, is reported and explained quantitatively for the first time. It is found that an increase of drain-to-spacer offset enhances the kink effect. That is to say, for devices with higher effective gate-drain channel resistance R gd connected in series to gate-drain capacitance, the kink effect is more prominent. The concept of dual-feedback circuit methodology [7] is used to simplify the circuit analysis of the small-signal model of RF power n-MOSFETs and then the output impedance of the devices is derived. The formula shows that the output impedance of the RF power n-MOSFETs follows a "shifted" constant resistance r circle at low frequencies, and then a "shifted" constant conductance g circle at high frequencies, which is in agreement with the experimental results. In addition, the kink effect in scattering parameter S 22 of RF power n-MOSFETs can also be interpreted in terms of poles and zeros [6]. That is to say, according to the two-pole approximation, S 22 have two poles and two zeros. It is proven that the two zeros fall between the two poles, and therefore, a dip can be observed in the Bode plot of ͉S 22 ͉.
DEVICE STRUCTURE AND S 22 VERSUS GATE-DRAIN RESISTANCEThe RF power n-MOSFETs studied in this paper were fabricated by 0.15 m CMOS technology. The n-MOSFETs with a gate length of 0.45 m and a total gate width of 500 m were divided into 50 fingers. The layout of the p-well contacts were designed as guard-rings to prevent the substrate coupling noise, and additional p-well contacts were butted with source contacts to reduce p-well resistance. The cross section of the n-MOSFET structure is schematically shown in Figure 1. Devices with drain-to-spacer offsets 0 m, 0.2 m, 0.4 m, 0.6 m, and 0.8 m were fabricated and studied. An additional N Ϫ implantation was done only at the drain side before the formation of a sidewall nitride spacer. After the source/drain formation, an oxide film was deposited and defined, which left an oxide film on the offset area to avoid the silicidation on this region during CoSi x formation. The low concentration of N Ϫ implantation and the long offset distance of N ϩ at drain terminal can reduce the electric field and impact ionization at the drain side. Therefore, the breakdown voltage can be improved. It showed that the drain breakdo...