A novel joint-in-via, flip-chip chip-scale package

Lee, T.K.; Zhang, S.; Wong, Chee Cheong; Tan, A.C.

doi:10.1109/ectc.2004.1319065

Cited by 3 publications

(1 citation statement)

References 20 publications

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“…Flip chip bonding, which is a general technique applying in CSP, SIP and PoP packages, has many merits compared to the most prevalent wire bonding technique. Joint-in-Via architecture provides a solution for the substrate to be used in flip-chip packaging [9]. The approach consolidates the landing pads, micro-vias, and flipchip joint into one common element, and circumvents the routing of Cu trace and pad landing.…”

Section: E Direct Flip-chip Bonding Architecturementioning

confidence: 99%

Ultra-fine via pitch on flexible substrate for high density interconnect (HDI)

Pun

Cui

Chung

2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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In the trend of miniaturization, low cost, and the performance of electronics, high density interconnect has been required for interfacing with very fine pitch BGA, CSP and SIP. This raises a great challenge to the substrate technology and related interconnect technology in electronic packaging for high density, small feature size and high performance. Miniaturization in electronics means finer lines and smaller vias in substrate technology. Very fine lines on the substrate are difficult to produce by thicker copper layer in conventional CO 2 laser blind via. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 μm, over the current blind via size of 50-200 μm by CO 2 laser drilling, is demonstrated on polyimide (PI) based flexible substrate. A via pitch at 30 μm for the blind via has been developed for next generation of stack die packaging accompanying with dimpless design, which ameliorates the void entrapment failure caused by soldering and direct flipchip (FC) bonding, and strengthens interfacial bond strength. In the meantime, thinner Cu conductor at top and bottom side could be achieved for high circuit density. The reliability of the ultra-fine blind vias has been assessed in daisy chain modules at substrate level, subjected to JEDEC air-to-air thermal cycle and thermal shock, and low/high temperature storage tests. Applications in direct FC bonding and their virtues including high electrical and thermal performances, and feasible of various metals surface finishing, will be discussed. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, stack die CSP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc Key Words: Blind via, High-density, flexible substrate, IC packaging. IntroductionLow cost, lightweight, handheld, multi-functional and high performance electronic products continue to challenge and drive the electronic packaging and assembly technology. As micro-systems continue to move toward for higher speed and micro-miniaturization, the demand for interconnection density both on the IC, package, and the substrate levels increase tremendously. Flexible HDI substrate is an emerging candidate that utterly fulfilled as-mentioned requirements, compared with conventional printed circuit board (PCB). Therefore, the demand of HDI Flex in high-tech electronic product is expected to grow at a tremendous rate [1,2]. Versatile and denser integrated circuit (IC) chip, and highdensity interconnect (HDI) substrate technology are striving.

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Section: E Direct Flip-chip Bonding Architecturementioning

confidence: 99%

Ultra-fine via pitch on flexible substrate for high density interconnect (HDI)

Pun

Cui

Chung

2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Bonding Development for Non-Conductive Paste (NCP)

Lee

Lua

Low

et al.

2005 7th Electronic Packaging Technology Conference

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Non-conductive paste (NCP) bonding offers fine pitch, simplified process, low packaging cost, and a lead-free interconnect system for flip-chip packaging. However, NCP bonding faces challenges in bonding yield rates. This paper studies bonding optimization through a closed-loop feedback system in order to understand the interaction of NCP materials with the bonding process for gold stud bumps on a rigid substrate. The bonding process is also correlated to conventional bonding study through differential [jgbl]scanning calorimetry (DSC) and macroscopic analysis of the interconnection structure. The study reveals that a significant temperature gradient exists across NCP materials between the die and the substrate, suggesting the existence of an optimal bonding temperature to activate the cross linking of the polymer. A certain threshold force is necessary to provide good physical contact between the gold studs and the bonding pads due to the co-planarity of the bumps. Sufficient dwell time is also necessary to ensure the joints remain in contact while the NCP material is cross linked. This approach simplifies the bonding process for flip-chip assembly.

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