A novel layout decomposition algorithm for triple patterning lithography

Fang, Shao-Yun; Chang, Yao-Wen; Chen, Wei-Yu

doi:10.1145/2228360.2228579

Cited by 50 publications

(23 citation statements)

References 6 publications

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“…We choose GUROBI [23] as the integer linear programming (ILP) solver, and CSDP [24] as the SDP solver. The benchmarks in [4,8] are used as our test cases. We scale down the Metal1 layer to 20nm half pitch.…”

Section: Resultsmentioning

confidence: 99%

“…The definition of cut can be extended to 2cur (3-cut), which is a double (triplet) of edges whose removal would disconnect the graph. However, different from the 1cut and 2-cut detection that can be finished in linear time [8], 3-cut detection is much more complicated. In this subsection we propose an effective 3-cut detection method.…”

Section: Gh-tree Based 3-cut Removalmentioning

confidence: 99%

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Layout decomposition for quadruple patterning lithography and beyond

Pan

2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this paper, we propose a generic and robust layout decomposition framework for QPL, which can be further extended to handle any general K-patterning lithography (K>4). Our framework is based on the semidefinite programming (SDP) formulation with novel coloring encoding. Meanwhile, we propose fast yet effective coloring assignment and achieve significant speedup. To our best knowledge, this is the first work on the general multiple patterning lithography layout decomposition.

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Section: Resultsmentioning

confidence: 99%

Section: Gh-tree Based 3-cut Removalmentioning

confidence: 99%

Layout decomposition for quadruple patterning lithography and beyond

Pan

2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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“…[4] and Ref. [10]. The width threshold w th , which is used in end-cut candidate generation, is set as dis m .…”

Section: Resultsmentioning

confidence: 99%

Triple patterning lithography (TPL) layout decomposition using end-cutting

Yu¹,

Gao²,

Pan³

2013

SPIE Proceedings

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Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and endcut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the conflict number and the stitch number.

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“…In general, there exist two types of MPL, Litho-Etch-Litho-Etch (LELE) type and self-aligned type. LELE-type of MPL allows stitch insertions and two-dimensional patterns [27], [59], [70], [71], [77], but coloring and overlay compensation schemes become extremely complicated for triple patterning lithography and beyond [12], [15], [30], [38], [60], [73], [76], [81]. Self-aligned type of MPL can minimize electrical variations from overlay and line-edge-roughness but introduces complex coloring and line-end constraints [40], [42], [56].…”

Section: Introductionmentioning

confidence: 99%

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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A novel layout decomposition algorithm for triple patterning lithography

Cited by 50 publications

References 6 publications

Layout decomposition for quadruple patterning lithography and beyond

Layout decomposition for quadruple patterning lithography and beyond

Triple patterning lithography (TPL) layout decomposition using end-cutting

Toward Unidirectional Routing Closure in Advanced Technology Nodes

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