A novel low gate-count serializer topology with Multiplexer-Flip-Flops

Tsai, Wen-Fa; Chiu, Ching-Te; Wu, Jen-Ming; Hsu, Shawn S. H.; Hsu, Yarsun; Tsao, Ying-Fang

doi:10.1109/iscas.2012.6271795

Search citation statements

Order By: Relevance

Paper Sections

Select...

Cross Talk2

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2013

2014

Publication Types

Select...

Other2

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(2 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To analyze the effect of neighboring TSVs on each other an accurate model for TSVs is required. Different models for TSVs have been proposed in [4] [6]. The RLC model used in our study is shown in Fig.…”

Section: Cross Talkmentioning

confidence: 99%

“…Typically, the area of the serializer and deserializer is very small compared to the TSV footprint and reducing the number of TSVs considerably saves area which makes the power consumption the only real drawback of this approach. A tree-type serilazer/deserializer [4] is designed in 65 nm CMOS technology that can operate at up to 10 GHz serial clock frequency. The structure of the serializer is shown in Fig.…”

Section: Cross Talkmentioning

confidence: 99%

See 1 more Smart Citation