A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Touiza, Maamar; Ochoa-Ruiz, Gilberto; Bourennane, El-Bay; Guessoum, Abderrezak; Messaoudi, Kamel

doi:10.1016/j.micpro.2012.07.004

Cited by 9 publications

(4 citation statements)

References 14 publications

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“…In order to make the relocation process less costly in terms of modification time, we make use of the OORBIT methodology (for Off-line/On-line Relocation of Bitstreams), based on a combination of off-line and on-line PBR approaches [6]. For the off-line stage, we have developed a tool that enables us, in the first place, in the analysis of the bitstreams obtained through the PR Design Flow.…”

Section: Deployed Relocation Methodologymentioning

confidence: 99%

“…However, PBR can most important aspect is to keep the relocation time overhead as low as possible, given that DPR systems suffer already of a time penalty introduced by the reconfiguration process. In this paper we introduce a comparative study carried out by using the OORBIT methodology [6], and comparing the relocation times with previous approaches, to demonstrate its advantages in the context of many-core applications.…”

Section: Introductionmentioning

confidence: 99%

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A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

Ochoa-Ruiz

Touiza

Bourennane

et al. 2013

2013 International Conference on Control, Decision and Information Technologies (CoDIT)

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Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module... However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time overhead might proof prohibitive. In order to find the best compromise between these approaches, we make use of the OORBIT tool (Offline /Online Relocation of Bitstreams) which helps us to accelerate the PBR considerably. In this paper, we compare the developed tool to others in previous works, specifically in the context of many-core applications; we give a particular importance to the reduction in the relocation time, which must to increase the time overhead already incurred by using partial reconfiguration. In this paper, we show how the tool has been used in this context, and a comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation process more amenable.

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Section: Deployed Relocation Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

Ochoa-Ruiz

Touiza

Bourennane

et al. 2013

2013 International Conference on Control, Decision and Information Technologies (CoDIT)

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“…In some cases for the Virtex architecture, it is necessary to make bitstream modifications to the stored task (such as a new CRC) if it is moved to a different on-chip location, even if the logic resources in the original and destination locations exactly match. Touiza, et al [15] provide a high-throughput method for moving a task from one region to another with a single bitstream by calculating most of the needed changes offline.…”

Section: Related Workmentioning

confidence: 99%

FPGA architecture support for heterogeneous, relocatable partial bitstreams

Huriaux

Sentieys

Tessier

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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The use of partial dynamic reconfiguration in FPGA-based systems has grown in recent years as the spectrum of applications which use this feature has increased. For these systems, it is desirable to create a series of partial bitstreams which represent tasks which can be located in multiple regions in the FPGA fabric. While the transferal of homogeneous collections of lookup-table based logic blocks from region to region has been shown to be relatively straightforward, it is more difficult to transfer partial bitstreams which contain fixed-function resources, such as block RAMs and DSP blocks. In this paper we consider FPGA architecture enhancements which allow for the migration of partial bitstreams including fixed-function resources from region to region even if these resources are not located in the same position in each region. Our approach does not require significant, time-consuming place-and-route during the migration process. We quantify the cost of inserting additional routing resources into the FPGA architecture to allow for easy migration of heterogeneous, fixed-function resources. Our experiments show that this flexibility can be added for a relatively low overhead and performance penalty.

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“…It is implemented in software using Microblaze and a hardware module named ARC for accelerated relocation circuit. OOR-BIT in [7] is a tool that makes the relocation of a bitstream offline and online. The purpose of the first hardware part is to extract the original information about the original location in a bitstream and calculate the new information of the location and embed it the in bitstream.…”

Section: A Related Workmentioning

confidence: 99%

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

Hannachi¹,

Rabah²,

Jovanovic³

et al. 2014

2014 26th International Conference on Microelectronics (ICM)

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Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.

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A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Cited by 9 publications

References 14 publications

A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

FPGA architecture support for heterogeneous, relocatable partial bitstreams

Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems

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