A novel multi deposition multi room-temperature annealing technique via Ultraviolet-Ozone to improve high-K/metal (HfZrO/TiN) gate stack integrity for a gate-last process

Abstract

ALD HfZrO high-K fabricated by novel multi deposition multi annealing (MDMA) technique at room temperature in Ultraviolet-Ozone (UVO) ambient is systematically investigated for the first time via both physical and electrical characterization. As compared to the reference gate stack treated by conventional rapid thermal annealing (RTA) @ 600 o C for 30 s (with PVD TiN electrode), the devices receiving MDMA in UVO demonstrates: 1) more than one order of magnitude leakage reduction without EOT penalty at both room temperature and an elevated temperature of 125 o C; 2) much improved stress induced degradation in term of leakage increase and flat band voltage shift (both room temperature and 125 o C); 3) enhanced dielectrics break-down strength and time-dependant-dielectric-breakdown (TDDB) life time. The improvement strongly correlates with the cycle number of deposition and annealing (D&A, while keeping the total annealing time and total dielectrics thickness as the same). Scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS) analysis suggest both oxygen vacancies (V o ) and grain boundaries suppression in the MDMA treated samples are likely responsible for the device improvement. The novel room temperature UVO annealing is promising for the gate stack technology in a gate last integration scheme.

CLM effect for 28nm stacked HK nmosfets after DPN treatment with different annealing temperatures

“…To retard the non-uniform channel carrier transport and the Fermi-level pinning effect [9] influencing the threshold voltage (V T ), the metal-gate (MG) [10][11][12] process replacing the poly-gate process was used. Owing to the desired minimization of crystallization of gate dielectric harmful to gate leakage and related dielectric constant (kvalue), the gate-last [13][14][15] (GL) process was manipulated in this time. In addition, the adequately deposited impurity or stacked layer in Hf-based gate dielectric is a promising method to reduce the possibility of poly-or nanocrystallization of gate dielectric around 700 o C, which means that the crystallization temperature can be raised up more.…”

Device Performance and Reliability Improvement for MOSFETs With $\hbox{HfO}_{2}$ Gate Dielectrics Fabricated Using Multideposition Room-Temperature Multiannealing

“…A control ALD HfO 2 was annealed by RTP at 600 • C for 30 s in N 2 with traceable amount of oxygen [5]. The total ALD deposition cycles are kept constant to ensure that all samples are with a similar EOT [4]. A TiN electrode of ∼50-nm thickness was then deposited by sputtering and patterned.…”

“…Recently, we have reported that gate-last processed capacitors with HK/MG stack show superior performance after room-temperature multideposition multiannealing (MDMA) in ultraviolet ozone (UVO) ambient, which is mainly due to the healing of oxygen vacancies (V o ) and suppression of grain boundaries based on the scanning tunneling microscopy and X-ray photoelectron spectroscopy analysis [4]. In this letter, with the application of the newly developed UVO MDMA method on the HK/metal (HfO 2 /TiN) …”

Investigation of different post HK annealing impact on HK film property and device performance

“…There are many methods investigated to passivate the oxygen vacancy, like fluorine incorporation [6], post HK nitridation [7], and others [8,9]. Among them, post annealing is an practicable and effective way [10,11]. New challenges emerged when CMOS technology evolved into 28nm and beyond era, the high-k last process needs appropriate post-deposition treatment to cure the possible defects in the high-k stack and compatible with silicidation low thermal budget restriction.…”