A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

Abstract

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of singlegate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.Index Terms-Field-effect transistor, multiple gate (MG), nanowire (NW), poly-Si. R ECENTLY, we proposed a new field-effect transistor structure which utilizes poly-Si nanowire (NW) as the channels [1], [2]. Fabrication of such device is very simple and requires no advanced lithography tools to generate the nanoscale patterns. Nevertheless, the fine-grain structure of poly-Si NW is considered to affect the carrier transport and device performance. Several ways are possible to relax such concern. One of that is to enhance the film crystallinity by implementing available schemes such as metal-induced lateral crystallization in the fabrication [3]. An alternative strategy is the adoption of multiple-gated (MG) configuration to increase the gate controllability over the channel. This has been widely demonstrated in the literature for devices with doublegate (DG) [4] and triple-gate [5], as well as surrounding-gate schemes [6]. Since poly-Si NWs are with a tiny volume and, thus, a limited amount of defects are contained, MG configuration is also expected to significantly improve the performance of poly-Si NW devices performance. The MG configuration may consist of several separate gates and each gate can be biased independently. Such design allows more freedoms for device operation [7].In this letter, a new MG structure which consists of an inverse-T-gate and a top-gate employed to surround the polySi NW channels is proposed. Top and cross-sectional views of the structure are shown in Fig. 1. From the figure, it can be understood that the poly-Si NW channels are almost fully surrounded by an inverse-T gate and a top gate. Moreover, the two gates can be biased independently to operate the device. Fig. 1. (a) Top and (b) cross-sectional views of the proposed MG FET device with poly-Si NW channels surrounded by an inverse-T gate and a top gate.Schematic flow of the fabrication process for the proposed device is shown in Fig. 2. First, silicon wafers were capped with a 100-nm-thick wet oxide. After depositing a 150-nm-thick in situ-doped n + poly-Si, the inverse-T gate was fabricated by twice standard G-line lithography and dry etching steps [ Fig. 2(a) and (b)]. This was followed by the deposition of a 20-nm-thick low-pressure chemical vapor deposition (LPCVD) oxide layer serving as the dielectric of inverse-T gate. A 100-nm-thick amorphous-...

Effects of independent double-gated configuration on polycrystalline-Si nonvolatile memory devices

“…11 Recently we had proposed several simple nanowire ͑NW͒ TFT preparation methods without the need of expensive lithographic tools. 12,13 In this paper, we extended the results of a previous work 14 and investigated the impacts of independent double-gated ͑IDG͒ configuration and the channel film thickness on the performance of TFT SONOS devices.…”

Insight into the performance enhancement of double-gated polycrystalline silicon thin-film transistors with ultrathin channel

“…However, as compared with the metaloxide-semiconductor transistors built on bulk-Si, a large amount of defects contained in the poly-Si channel film would dramatically aggravate the device performance in terms of high subthreshold swing ͑SS͒ and OFF-state leakage current. 1 Such concern can be relieved by thinning the channel to reduce the amount of defects 4,5 and/or the adoption of a multiple-gated configuration to enhance the gate controllability. [5][6][7] The latter approach has also been widely investigated in devices with monocrystalline Si channel.…”

“…1 Such concern can be relieved by thinning the channel to reduce the amount of defects 4,5 and/or the adoption of a multiple-gated configuration to enhance the gate controllability. [5][6][7] The latter approach has also been widely investigated in devices with monocrystalline Si channel. 8,9 By combining the above two approaches, SS smaller than 100 mV/dec can be achieved.…”

“…8,9 By combining the above two approaches, SS smaller than 100 mV/dec can be achieved. 5 On the other hand, there are a lot of theoretical studies devoted to analyzing the properties of traditional planar poly-Si TFTs, [10][11][12] but few reports were done on the poly-Si-based devices with multiple-gated configuration. Since the carriers transport in the poly-Si channel is mainly affected by the conduction barriers formed at the grain boundaries, 10 the impacts of multiple-gate driving on the transport properties are expected to exhibit some unique features.…”

Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

“…In addition, reduction of defect density and improvement of gate controllability via scale-down of the poly-Si NW channel have been reported. Some studies have even demonstrated the scale-down of the poly-Si NW without using advanced lithographic tools and have obtained excellent device characteristics [11]- [14]. Poly-Si NW TFTs with small gate length (< 0.1 μm) and very thin dielectrics have also been proposed to improved transfer characteristics [15], [16].…”