Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

Liu, Tung-Yu; Lo, Shen–Chuan; Sheu, Jeng−Tzong

doi:10.1109/led.2013.2247737

Cited by 11 publications

(14 citation statements)

References 16 publications

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“…A vertical structure is preferred, as it is difficult to fabricate GAA over lateral nanotube even with the use of a sacrificial layer (yellow electrode is used as core-source instead of gate; a shellsource electrode is omitted for the proposed devices) [19][20][21].…”

Section: Device Structuresmentioning

confidence: 99%

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Apoorva

Kumar

Amin

et al. 2021

IET Circuits, Devices & Systems

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Investigation and analysis of a ferroelectric material-based dopingless nanotube tunnel field-effect transistor are conducted using a lead zirconate titanate (PZT) gate stack to induce negative capacitance in the device. Landau-Khalatnikov equations are used in deriving the parameter values of the ferroelectric material to ensure accurate results. The nanotube structure of the tunnel field-effect transistor allows for better electrostatic control owing to its gate-all-around structure. Incorporation of negative capacitance further reduces the voltage supply requirement and power consumption of the structure while simultaneously improving switching. In addition, the device is studied for varying thicknesses of the dielectric PZT material. The threshold voltage of the device under study was calculated as 0.281 V, and the average subthreshold slope of the device was reduced to 18.271 mV/decade, far below the thermionic limit of 60 mV/decade. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Device Structuresmentioning

confidence: 99%

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Apoorva

Kumar

Amin

et al. 2021

IET Circuits, Devices & Systems

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“…[1][2][3][4] Despite the gate-all-around (GAA) structure that provides superior channel controllability, nonuniformity of dangling bonds and grain boundaries in the poly-Si nanowire (NW) channel usually undermine the carrier mobility and device switching speed. Poly-Si TFTs utilizing a NW channel with multiple-gate structures have been demonstrated to meet demands in electrical characteristics.…”

confidence: 99%

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Tso¹,

Liu²,

Sheu³

2015

Jpn. J. Appl. Phys.

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Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; >124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 + 13 mV/V), and a high I ON /I OFF current ratio (>1 ' 10 9 ) under a relatively low voltage condition (V D = 0.3 V, V G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

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“…Over the past years, polysilicon nanowires (NWs) have been widely investigated for the potential applications like high performance surround gate polysilicon NW thin film transistors (TFT) [1][2][3][4], innovative memory devices [5][6][7][8], excellent thermoelectric performance [9][10][11] and for promising biosensing applications [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

“…Polysilicon nanowire has been shown to demonstrate a record low thermal conductivity [11] and also has been applied for high sensitivity, real-time and label-free detection of diverse biological targets like inflammatory biomarkers, DNAs, miRNAs, proteins, SARS-Co-V2 etc [12][13][14][15][16][17]. Polysilicon nanowires are usually realized by using thin film technology and spacer etch technique [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] (figure 1). Use of mature lithography and industry standard deposition/spacer etch techniques make this technology potentially attractive.…”

Section: Introductionmentioning

confidence: 99%

“…In this technology, polysilicon nanowires can be fabricated on glass or plastic substrates which may enable flexible foil electronics, affordable disposable diagnostics and portable, wearable and/or implantable sensors. However, no mask protection is used during spacer etch and hence, the dry etch plasma affects the corner of the nanowire thereby results in the quarter circle shaped NW and sidewall striations [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. As a result, it is difficult to control volume of the nanowire across the wafer and hence, the degraded uniformity may severely affect the manufacturability of the process.…”

Section: Introductionmentioning

confidence: 99%

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Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

Hakim

2023

Eng. Res. Express

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We report a low-cost mass manufacturable route for polysilicon nanowire (NW) fabrication through comparative investigations of spacer etch techniques to realize nanowires from amorphous silicon (α-Si) layer. The process uses thin film technology and mature top-down microelectronics (linewidth > 10 µm). Anisotropic deep silicon etch process using the elevated plasma density of high-density low-pressure systems (HDLP) with a simultaneous flow of etchant SF6 and inhibitor C4F8 delivered nanowires with quarter circle shape. The nanowires are also characterized with significant sidewall striations and noticeable aggregation of polymers. HDLP etch system with a sequential flow of etchant SF6 and inhibitor C4F8 delivered a near rectangular nanowire shape. However, the generally good profile is marred with significant sidewall striations and accumulation of polymers at the tip of the etched sidewall. Shallow etch process using low density plasma in a cheap capacitively coupled reactive ion etch (RIE) equipment with a simultaneous flow of etchant SF6 and inhibitor O2 delivered nanowires with ideal rectangular shape. The nanowires have hardly visible sidewall striations and/or polymer. These results indicate that deep silicon HDLP etch processes albeit advanced and costly are not suitable for good quality nanowire definition using spacer etch from a thin film of α-Si layer. Low density plasma process with simultaneous flow of SF6 and O2 gases in relatively cheap RIE system provides high quality nanowires and hence, provides a simple, low cost, wafer scale mass manufacturable route for high quality polysilicon nanowire fabrication.

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Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

Abstract: Abstract-

Cited by 11 publications

References 16 publications

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Design and investigation of negative capacitance–based core‐shell dopingless nanotube tunnel field‐effect transistor

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Comparative investigation of anisotropic etches for polysilicon nanowire definition in thin film technology

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