A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications

Yeh, Chih-Ting; Wang, Tahui; Tsai, Wen-Jer; Lu, Tsung-Chien; Chen, Ming-Shiang; Liao, Yi-Ying; Ting, W.; Ku, Yen-Hui Joseph; Lu, Chih‐Yuan

doi:10.1109/ted.2005.845085

Cited by 6 publications

(1 citation statement)

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“…Commercially available SONOS memories have been developed as two-bitper-cell applications for high-density NVM memories [5]- [8]. Novel operating schemes such as PHINES offer improved performance [9]. Nevertheless, such SONOS devices are facing difficulties in two-bit separation, oxide-nitride-oxide downscaling, and reduction of processing complexity, as they proceed into the deep-submicrometer regime.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Jeng

Chia-Sung

Hon

et al. 2007

IEEE Trans. Electron Devices

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This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 µs, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance, are reported. Finally, the scalability of NOI devices is simulated and discussed. Index Terms-Charge trapping, nonoverlapped implantation (NOI), nonvolatile memory (NVM). Since 2005, he has beenan Associate Professor in the Department of Electronic Engineering, Chung Yuan Christian University with conducting research on surface acoustic wave sensors and semiconductor memories. His current research interests are in the areas of advanced CMOS processing technologies; characterization, simulation and modeling of deep-submicrometer nonvolatile memory devices and the cell array design for nonvolatile memory applications.

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Section: Introductionmentioning

confidence: 99%

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Jeng

Chia-Sung

Hon

et al. 2007

IEEE Trans. Electron Devices

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Flash‐Type Memories

Mikolajick¹

2010

Nanotechnology

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The trend toward more mobile applications drives a rapidly increasing demand for non‐volatile memories. Today, Flash‐type non‐volatile memories offer by far the best trade‐off between cost and performance. In this chapter, Flash concepts relevant to today and the future are reviewed. Following a brief introduction to the market and the history of Flash memories, the basics required to understand the concepts of Flash memory concepts are explained. These mechanisms are involved in charging and discharging the charge storage layer, as well as the architecture used to combine many cells into large memory arrays. The third section details today's mainstream Flash concepts, which are based on the floating‐gate cell, outlines the physics of the floating‐gate transistor, and introduces the concepts of NOR and NAND Flash. Finally, the main reliability‐determining effects are reviewed, and the further scaling path of floating‐gate memories is illustrated. One way of overcoming the limitations of floating‐gate memories is to replace the conductive floating gate with an insulating charge‐trapping layer; hence, the conventional silicon‐oxide‐nitride‐oxide‐silicon (SONOS) cell and its trade‐offs are explained. Multi‐bit charge trapping, a concept recently introduced for both code and data Flash applications is described in detail, and the scaling of charge‐trapping Flash devices is discussed. Finally, a brief introduction is provided to nanocrystal Flash memory devices, which represent another way of overcoming some basic limitations of the floating gate.

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HfO2 Trap Layer Nonvolatile Flash Memory on SiGe Channel

Lin

You

et al. 2014

2014 International Symposium on Computer, Consumer and Control

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A Novel PHINES Flash Memory Cell with Low Power Program/Erase, Small Pitch, Two-Bits-Per-Cell for Data Storage Applications

Cited by 6 publications

References 13 publications

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Flash‐Type Memories

HfO2 Trap Layer Nonvolatile Flash Memory on SiGe Channel

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