Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Abstract

This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 µs, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance, are reported. Finally, the scalability of NOI devices is simulated and discussed. Index Terms-Charge trapping, nonoverlapped implantation (NOI), nonvolatile memory (NVM). Since 2005, he has beenan Associate Professor in the Department of Electronic Engineering, Chung Yuan Christian University with conducting research on surface acoustic wave sensors and semiconductor memories. His current research interests are in the areas of advanced CMOS processing technologies; characterization, simulation and modeling of deep-submicrometer nonvolatile memory devices and the cell array design for nonvolatile memory applications.

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

“…Although the HHI probability of the NOI device is less than that of the SONOS device, the charge required for programming and erasing (P/E) the NOI device is largely reduced owing to its low fringing capacitance in the NOI region, thus making the NOI device comparable to the SONOS device in the P/E speed. 12,13)…”

“…where ¦C fr denotes the local fringing capacitance. 12) After the fringing capacitance, local ¦V th , and ¦x are taken into account, the lateral charge trapping distribution can be determined for each lateral position x (Fig. 15).…”

“…10,11) Among them, the spacer-trapping n-type MOSFET with gate-to-source/drain non-overlapped implantation (NOI) has been studied in terms of electrically erasable programmable read-only memory (EEPROM)/ mask read-only memory (MaskROM)/antifuse operations, cycling, retention, scaling, and electron distribution. [11][12][13][14][15] NOI MOSFETs are fully compatible with industrial CMOS fabrications even without modifying the process or increasing mask tooling cost. Stored electrons are trapped in the silicon nitride spacer by channel hot electron injection (CHEI) in the NOI channel near the drain junction.…”

Non-overlapped implantation (NOI) MOSFET synapse and its implementation on supervised neural network

“…NOI MOSFETs are known for their applicability in various nonvolatile memory (NVM) functions [1][2][3][4][5][6]. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using pure logic processing.…”

Single-electron injections in fringing-field-induced charge-trapping memories

“…This novel MOSFET with gate-to-drain NOI is an NVM device capable of storing multiple bits per transistor and its device processing is simple and fully compatible with standard logic CMOS fabrication processes as compared to other SONOS devices. Unlike other SONOS-based NVM devices, the scaling risk of two-bit charge merging can be avoided in NOI devices because the two bits in a NOI device are stored in two different SiN spacers, which are physically separated by the gate electrode and gate oxide [8][9][10][11].…”