A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Morikawa, Yasuhiro; Murayama, Takahide; Sakuishi, Toshiyuki; Yoshii, Manabu; Suu, Koukou

doi:10.1109/ectc.2012.6248923

Cited by 20 publications

(5 citation statements)

References 5 publications

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“…However, the elimination of the scallop is challenging because the improvement of figureof-merits evaluating the etching performance has tradeoffs. For instance, a 'scallop-free' microstructure with good depth uniformity has been reported, but the profile is poor with low verticality or a bowling structure [34]. As for our work, regardless of how the etch uniformity changes, the scallop sizes are all as small as <100 nm.…”

Section: Resultsmentioning

confidence: 48%

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

Cui¹,

Jian²,

Chen³

et al. 2019

J. Micromech. Microeng.

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The formation of various deep silicon structures using plasma etching has wide applications in sensors, micro-electro-mechanical systems and 3D wafer level integration. However, the fabrication of silicon cavities with high accuracy at depth within a large wafer size is still a challenge due to the large amount of etching required. Herein, silicon cavity etching uniformity approaching 3% in a depth of ~100 µm on a 12-inch wafer is achieved through tuning the focus ring height, baffle shape, double zone helium cooling system and chamber pressure. The simulation of the electromagnetic field and gas flow field separately provides the guidance for the improvement, and the way in which the wafer temperature influences the etch uniformity is demonstrated. These results have significance for both the understanding of the plasma etching mechanism and the practical application of the silicon etching process for advanced device fabrication.

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Section: Resultsmentioning

confidence: 48%

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

Cui¹,

Jian²,

Chen³

et al. 2019

J. Micromech. Microeng.

View full text Add to dashboard Cite

show abstract

“…The etcher system is using NLD (magnetic Neutral Loop Discharge) plasma that is a kind of high electron density ICP (Inductive Coupling Plasma). This plasma etch system can be used for oxide, Si and polymer, for very uniform etching, respectively [2,3,4]. In this paper, study on direct (non Bosch) Si etch method to get a smooth sidewalls with no scalloping and a good control of the etched profile using new ICP plasma source.…”

Section: Introductionmentioning

confidence: 99%

“…"Scallop-free" etching process has developed for TSV fabrication [2]. As a result, the smooth-sidewall had proved shorten PVD process time [3]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper.…”

mentioning

confidence: 99%

Novel TSV process technologies for 2.5D/3D packaging

Morikawa

Murayama

Sakuishi

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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2.5D silicon interposers" and "Hetero 3D stacked" technology for high-performance LSI are gathering the most attention from now on. These technologies can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked each function devises. 2.5D and hetero-3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the long-term reliability of TSV production is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. "Scallop-free" etching process has developed for TSV fabrication [2]. As a result, the smooth-sidewall had proved shorten PVD process time [3]. At first, it investigated a cost correlation of taper-shape etching and Cu-ECP (electrochemical plating) in this paper. And then, a polyurea film using a vapor deposition polymerization technology (which is Ulvac's FPF/PV large panel technology) tried introduction as isolation liner for next-generation high frequency device. And, it performed the film formation to a TSV pattern. IntroductionIn order to realize the manufacturing and cost benefits of via last technology for the 3D stacked integration, creation of TSV spanning all layers of fully formed chips must be realized. This is particularly new etching method challenging for TSV devices. The etcher system is using NLD (magnetic Neutral Loop Discharge) plasma that is a kind of high

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“…Nowadays, most of the semiconductor researchers make efforts to minimize or even eliminate the scallop nanostructure. Morikawa et al [17] attempted to eliminate the scallop nanostructure in deep silicon etching by magnetic neutral loop discharge plasma technology. Voss et al [18] added C 4 F 8 in the etch step of the Bosch process to achieve a scallop-free and vertical structure.…”

Section: Introductionmentioning

confidence: 99%

The application of the scallop nanostructure in deep silicon etching

et al. 2020

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Micro/nanostructures with high aspect ratios in silicon wafers obtained by plasma etching are of great significance in device fabrication. In most cases, the scallop nanostructure in deep silicon etching should be suppressed. However, the scallop nanostructure could be applied in electronic device fabrication as characteristic information, which indicates the balance between deposition and etching. In this work, the applications of scallop nanostructures in etching process optimization and environmental protection are demonstrated. In addition, the minimum effect of the cycle time on the scallop size is reported for the first time. These results could bring new thoughts to the electronic devices related fields, such as micro-electro-mechanical systems (MEMS), silicon capacitors and advanced packaging.

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A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Cited by 20 publications

References 5 publications

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

Uniformity improvement of deep silicon cavities fabricated by plasma etching with 12-inch wafer level

Novel TSV process technologies for 2.5D/3D packaging

The application of the scallop nanostructure in deep silicon etching

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