A Novel Self-Aligned Offset-Gated Polysilicon TFT Using High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Dielectric Spacers

Xiong, Zhibin; Liu, Haitao; Zhu, Chunxiang; Sin, J.K.O.

doi:10.1109/led.2004.825206

Cited by 17 publications

(7 citation statements)

References 5 publications

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“…[7][8][9][12][13][14] Additionally, hot carrier stress was carried out at V DS = 10 V and V GS = 5 V for 2000 s to examine the device reliability. Figure 6a and b shows the degraded transfer characteristics of T-gate TFTs and conventional TFTs with various stress times, respectively.…”

Section: G348mentioning

confidence: 99%

A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode

Liao

Chien

et al. 2006

Electrochem. Solid-State Lett.

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A T-shaped-gated ͑T-gate͒ poly-Si thin-film transistor ͑TFT͒ with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics.

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Section: G348mentioning

confidence: 99%

A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode

Liao

Chien

et al. 2006

Electrochem. Solid-State Lett.

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“…Using a high dielectric (high-k) material to conduct electric field and induce electron have been proposed [7,8]. In this study, we propose a new DGMOSFET including a p-region and a silicon-nitride layer to carried out a low Q GD device without complex process flow and overcome the problems mentioned above.…”

Section: Introductionmentioning

confidence: 99%

Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

Liao¹,

Chien²,

Lin³

et al. 2009

Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials

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“…A thicker dielectric layer under the subgate composed of oxide/nitride/oxide films reduces the drain electric field. The damascene process is much more complicated than other FID formation processes such as HfO spacers [5]. However, we can easily control the nitride, oxide, and poly-Si in many processes, such as deposition, dry and wet etching, and polishing.…”

Section: Introductionmentioning

confidence: 99%

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

Park

Kim

2005

IEEE Electron Device Lett.

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We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the ON state, an inversion layer is induced by the subgate as a drain so that the ON current is still high and the poly-Si region under the subgate behaves as an offset, reducing the OFF-state leakage current during the OFF-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum OFF-state leakage current of the new TFT is decreased from 1 4 10 10 to 1 3 10 11 without sacrifice of the ON current. In addition, the ON-OFF current ratio is significantly improved.Index Terms-Chemical-mechanical polishing (CMP), damascene, field-induced drain (FID), thin-film transistor (TFT).

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A Novel Self-Aligned Offset-Gated Polysilicon TFT Using High-<tex>$kappa$</tex>Dielectric Spacers

Cited by 17 publications

References 5 publications

A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode

A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode

Reducing the Gate Charge of Dual Gate Power VDMOSFET by Pseudo-Gate

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

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