A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs

Ichige, M.; Takeuchi, Yoshinori; Sugimae, K.; Sato, Akira; Matsui, M.; Kamigaichi, T.; Kutsukake, H.; Ishibashi, Yukio; Saito, Masato; Mori, S.; Meguro, H.; Miyazaki, S.; Miwa, Takaki; Takahashi, Sadao; Iguchi, Tomohiro; Kawai, N.; Tamon, Susumu; Arai, Norihisa; Kamata, Hiroshi; Minami, T.; Iizuka, H.; Higashitani, M.; Pham, Trung; Hemink, G.; Momodomi, M.; Shirota, R.

doi:10.1109/vlsit.2003.1221100

Cited by 9 publications

(5 citation statements)

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“…The V th level of the neighboring cells is changed due to FG-FG coupling. 15,16) Figure 6 illustrates the write order and V TH distribution of TLC NAND flash memories. In TLC NAND flash memories, before the precise write in the verify programming, the rough write to neighboring cells should be carries out to prevent FG-FG coupling effect.…”

Section: Tlc Nand Flash Memory Basicsmentioning

confidence: 99%

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

Hachiya

Koh

Miyaji

et al. 2014

Jpn. J. Appl. Phys.

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This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

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Section: Tlc Nand Flash Memory Basicsmentioning

confidence: 99%

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

Hachiya

Koh

Miyaji

et al. 2014

Jpn. J. Appl. Phys.

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“…The FG-FG coupling increases the V TH of the neighboring memory cells [21][22][23]. These mechanisms cause the increment of program-disturb error.…”

Section: A Analyses Of Error Rate Of Each V Th State For Program-dismentioning

confidence: 99%

A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Doi

Tanakamaru

Takeuchi

2014

Solid-State Electronics

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An optimized asymmetric coding strategy is proposed to improve the reliability of the NAND flash memories. The previously reported asymmetric coding reduces the dataretention error by decreasing the population of the V TH state which has higher error rate, and is measured on 4Xnm NAND flash memory [1]. In [2], by increasing the number of the lowest V TH state, the proposed asymmetric coding strategy reduces the V PGM disturbance, and alleviates the floating-gate (FG)-FG coupling. And also, the program-disturb bit error rates (BERs) in 2Xnm, 3Xnm, and 4Xnm NAND flash memories are reduced by 71%, 73%, and 89%, respectively. In this paper, the effect of asymmetric coding on the data-retention error is investigated in 2Xnm NAND flash memory. From the measured results, the proposed asymmetric coding effectively increases the population of the lowest V TH state which has no data-retention error. The data-retention BERs in 2Xnm, 3Xnm and 4Xnm NAND are decreased by 17%, 52% and 70%, respectively.Keywords: NAND flash memory, asymmetric coding, reliability, program disturb error, dataretention error M. Doi et al., " A Scaling Scenario of Asymmetric Coding to Reduce Both Data Retention and Program Disturbance of NAND Flash Memories" 3 / 15 I.

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“…The coupling ratio is obtained by using top and sidewall of floating gate, and the interference between floating gates is effectively suppressed by this control gate shielding between adjacent cells. This approach also involves three-dimensional use of cell [11][12][13].…”

Section: Nand Flash Memorymentioning

confidence: 99%

Advanced memory concepts for DRAM and nonvolatile memories

Horiguchi

2006

Solid-State Electronics

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A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs

Cited by 9 publications

References 0 publications

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

Hybrid triple-level-cell/multi-level-cell NAND flash storage array with chip exchangeable method

A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Advanced memory concepts for DRAM and nonvolatile memories

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