A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG and p-pillar shielding regions are introduced to form an effective two-level shielding, which reduces the specific gate-drain charge (Q
gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. A p-pillar shielding region surrounded thick oxide efficiently protects gate oxide from peak electric field, thereby increasing the breakdown voltage (BV). Additionally, because of the high concentration on the n-type drift region, the electrons diffuse rapidly and the specific on-resistance (R
on,sp) becomes smaller. In the end, compared with the bottom p+ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV2/R
on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R
on,sp×Q
gd,sp) is significantly improved by 310%, respectively.