A Novel SRAM PUF Stability Improvement Method Using Ionization Irradiation

Zhang, Xu; Jiang, Chunsheng; Gu, Ke; Zhong, Le; Fang, Wen Hai; Dai, Gang

doi:10.3390/electronics9091498

Cited by 7 publications

(3 citation statements)

References 24 publications

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“…Also, if error correction codes are used, usually implementing helper data algorithms (HDAs), the chances of a secure key being tampered are increased [12]. Furthermore, environmental conditions like temperature, aging or radiation can affect the result because they can modify cell reliability, either by worsening or even improving it [26][27][28].…”

Section: Sram Pufsmentioning

confidence: 99%

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

et al. 2022

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This work proposes a methodology to estimate the statistical distribution of the probability that a 6T bit-cell starts up to a given logic value in SRAM memories for PUF applications. First, the distribution is obtained experimentally in a 65-nm CMOS device. As this distribution cannot be reproduced by electrical simulation, we explore the use of an alternative parameter defined as the distance between the origin and the separatrix in the bit-cell state space to quantify the mismatch of the cell. The resulting distribution of this parameter obtained from Monte Carlo simulations is then related to the start-up probability distribution using a two-component logistic function. The reported results show that the proposed imbalance factor is a good predictor for PUF-related reliability estimation with the advantage that can be applied at the early design stages.

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Section: Sram Pufsmentioning

confidence: 99%

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

et al. 2022

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“…SRAM PUFs have drawn a lot of interest both in academia and industry [5] because they can take advantage of already existing SRAM cells in an IC, reducing the implementation cost. An SRAM PUF response is defined by the power-up logic value of a set of SRAM cells, which may settle at 1 or 0 depending on the inherent bias generated during its fabrication.…”

Section: Introductionmentioning

confidence: 99%

A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array

Santana-Andreo,

Saraza-Canflanca,

Carrasco-Lopez

et al. 2023

2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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The use of SRAM power-up values is the foundation of one of the most common Physical Unclonable Functions (PUFs) implementations, providing a Root-of-Trust for cryptographic applications at a low cost. PUFs are required to return the same response each time it is requested. However, SRAM power-ups by themselves are not reliable enough for the demanding PUF applications. This problem is solved by a variety of techniques that rely on an expected baseline reliability, extracted from tests performed under process, voltage and temperature variations. Nevertheless, aging effects, specifically Bias Temperature Instability (BTI), can have a significant impact that may not conform to the said baseline and are often ignored or overlooked due to the difficulty in properly characterizing and modeling them. In this work, we employ our custom chip specifically made to facilitate the characterization of aging through stress, i.e., applying a supply voltage larger than the nominal voltage to accelerate the impact of BTI and thus provide a more detailed look into the behavior of aging in an SRAM PUF array.

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“…Thus, nano-scale CMOS circuits are more vulnerable to errors, such as the Soft Error (SE) caused by Single Event Upset (SEU) [1]. These errors have a huge negative impact on hardware security of integrated circuits, which is invested frequently [2,3], even for electronic applications [4][5][6]. In the particular case of SE, they have to be addressed as a hardware security or hardware reliability issue since they can be caused by and from the environment.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

et al. 2021

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In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

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A Novel SRAM PUF Stability Improvement Method Using Ionization Irradiation

Cited by 7 publications

References 24 publications

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram

A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

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