A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

Tabrizchi, Sepehr; Azimi, Nooshin; Navi, Keivan

doi:10.1631/fitee.1500366

Cited by 21 publications

(11 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The third group is band-to-band tunneling CNTFETs. These transistors have higher cutoff characteristics and low ON currents, and also they are very appropriate for designing ultra-low power and sub-threshold circuits [17].…”

Section: Laser Ablation Methodsmentioning

confidence: 99%

“…A multiplier circuit in CNTFET technology that used design approach of multi-value logic is offered in [16]. In [17], several designs of half adder and multiplier using ternary logic are presented. In this work, results of the simulation have shown that the proposed circuits have low power consumption and high speed; also in these circuits area is being reduced.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

Shaveisi

Rezaei

2020

BioNanoSci.

View full text Add to dashboard Cite

It is obvious that the design of low power digital circuits is very important. Hence, reversible logic can be used as the great method for reducing power consumption. In this paper, we attempt to present various CNTFET-based reversible combinational circuits such as multiplexers and decoders by simultaneous use of the reversible Fredkin gate and Gate Diffusion Input (GDI) technique. At first, we illustrate the block diagram of multiplexers and decoders according to the definition of reversible gates. Then, we introduce the design approach of CNTFET-based circuits by using the GDI technique. All structures are simulated using Synopsys HSPICE with standard 32 nm CNTFET technology in various conditions including temperature 27°C, simulation time from zero to 100 ns, and other parameters are the variable. In this work, we investigate the variation effect of supply voltage, temperature, number of nanotubes, and chiral vector in performance evaluation of the mentioned circuits. In addition, the ECPOT analysis is reported. According to the results, the proposed CNTFET-based reversible multiplexers achieve a significant saving in average power consumption (approximately 99.99% for 2:1 multiplexer, 99.95% for 4:1 multiplexer, 99.96% for 8:1 multiplexer compared with the best previous work) and the average power consumption for 16:1 multiplexer is 25.47 nw. The proposed CNTFET-based reversible decoders have high performance in the average power consumption (approximately 99.99% for 2:4 decoder, 99.99% for 3:8 decoder, and 99.22% for 4:16 decoder compared with the best previous work). Moreover, applying these suggested circuits significantly improves the speed, PDP, and EDP of complex arithmetic structures.

show abstract

Section: Laser Ablation Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

Shaveisi

Rezaei

2020

BioNanoSci.

View full text Add to dashboard Cite

show abstract

“…(5) Use transmission gates (TGs) in series, special transistors arrangements, or Resistive Random Access Memory (RRAM) such as: Authors of [28], [29] proposed THAs with (39 and 50 CNT-FETs) and TMULs with (34 and 38 CNTFETs) using cascading TGs, which produced higher propagation delays and PDP. In [30], the authors proposed THA with 90 CNTFETs and TMUL with 62 CNTEFTs using RRAM.…”

Section: A Literature Reviewmentioning

confidence: 99%

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

2021

View full text Add to dashboard Cite

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

show abstract

“…Electrical characteristics of each CNFET depend on a vector called chiral vector that is specified by

false(n_{1}, n_{2} false)

. Each indices of this vector determines the rolling direction of graphene sheet and tube axis [17–23]. For example, if

n_{1} - n_{2} \neq 3 k

( k is an integer) SWCNT has semiconductor features and otherwise is conductive [24].…”

Section: Carbon Nanotube Field‐effect Transistorsmentioning

confidence: 99%

Method for designing ternary adder cells based on CNFETs

Tabrizchi

Panahi

Sharifi³

et al. 2017

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-V t circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select successor and predecessor of input trits for the output node values. This study describes the novel ternary multiplexer, successor and predecessor cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

show abstract

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

Cited by 21 publications

References 20 publications

Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

Design and Implementation of CNTFET-Based Reversible Combinational Digital Circuits Using the GDI Technique for Ultra-low Power Applications

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Method for designing ternary adder cells based on CNFETs

Contact Info

Product

Resources

About